Need For Unified Chip-Package Analysis

For anyone involved in the system-on-chip (SoC) design cycle over the past few years, it is easy to see that the functionality of the chip has become more diverse with the addition of new features and duplication of main functions to drive higher throughput. This trend coupled with the need to maintain low power through various techniques such as voltage islands and power and clock gating have caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in the chip that adversely affects the operation of the SoC.

Power integrity analysis ensures that the voltage seen by individual transistors is as robust as possible across all operating modes of the chip. However, the increasing sophistication of the SoCs and the underlying semiconductor processing technologies has made analysis more complex and demanding. In addition, the inclusion of package and PCB parasitics in the SoC power integrity analysis has become a standard practice, yet the model of the package (and the PCB) used for the analyses and sign-off tend to lack several of the required elements.

Due to the increasing size of the SoCs and the variation in the switching current and parasitic profile across the chip, the individual connections between the SoC and the package at the C4 bump level need to be as granular as possible. The traditional approach of grouping the bumps either into a ‘lumped’ connection or through geometric grouping such as 4×4 or 6×6 does not provide the granularity required for accurate time-domain simulation. In addition, the parasitics associated with the various power and ground networks (or domains) should be kept separate, and the package parasitic elements should not be constrained to represent only a specific current return path. It should have all the degrees of freedom needed to model any return path.

These aspects are required for simulating each individual power or ground domain to achieve a more realistic voltage gradient across the die. During the SoC power integrity analysis step it is important to bring in accurate and appropriate models of the package into the chip-level simulation, as well as having visibility into how the activity inside the chip affects the current flow in the package interconnect structures and hence the design of the package. Let us look into these in more detail.

Benefits of a high bump resolution SoC to package connection
The grouping of the connections between the package and the SoC affects a package-aware SoC power integrity analysis in the following way. Consider the on-chip switching current from logic operations with various frequency components. The high frequency parts are supplied by the on-chip decap because the package suppresses high-frequency current flow from the battery or the VRM. The change in charge on Cdie (local) determines the local drop (deltaV = deltaQ/C).

When the bumps are grouped together to form the connection between the chip and the package model, the entire chip capacitance is seen as a single total value by the package. The parts of the SoC that are not switching end up providing their capacitances to the active portions of the SoC due to artificial shorting. Hence, the noisy sections of the chip will appear to have more capacitance at their disposal to provide charge for the high frequency noise, whereas the quiet section will appear to have more charge moving on/off its local capacitance. This distorts the voltage variation across the die by uniformly reducing the voltage drop across the chip. The only variation seen is the voltage drop from power grid in individual sections of the chip.

With a distributed package model both the chip network and package network are providing impedance across the die, resulting in a more realistic voltage gradient. Bumps at the periphery of the chip will have higher impedance. And if the switching current is higher there, those areas will have higher drop at the bumps, while the center area of the chip with lower impedance will see lower drop at the bumps. This variation in the bump level voltage drop is more realistic and consistent with what is seen in reality.

Figure: Highlights voltage drop distribution of a chip for 3 types of analyses: a) without package (green), b) lumped package (blue), and c) distributed package (red). Simulation without package versus lumped package shows a shift in the distribution due to the package L. Simulation with lumped package model shows how distribution ‘tightens’ since the voltage drop is dominated by the package, whereas, the distribution remains the same for all cells in the chip due to the shorting of all C4 bumps in the analyses. Simulation with the distributed package connection shows some parts of the chip with higher drop due to greater package effect whereas some other parts have lower drop.

Benefits of a terminal based package model over a port based model.
Typically there are two types of package models used to represent the parasitics of the package structures. One type is the terminal-based RLCK model, and the other is a port-based S-parameter model. An RLCK model is a physical model and behaves in a more intuitive manner, whereas an S-parameter model—while providing a more broadband response—is not suitable for power integrity analysis needs.

These two types of models handle the parasitic elements of each net in the following way. In the RLCK model, a node representing a single terminal for a given net is connected to a voltage source, referenced to ideal ground, while a separate node, also on the same net, is connected to a dc current source, referenced to ideal ground. The voltage difference between the two nodes will equal the product of the current flow and the parasitic resistance between the two nodes, assuming all other nodes for the given net are floating and the network is passive. The connection to an S-parameter model is port-based, and therefore the parasitic effects from a given net cannot be isolated. Each port consists of two terminals. One terminal is the node of interest for a given net, and the other terminal represents a reference node. The reference node is typically placed on the ground supply network. The S-parameter model only shows the voltage differences across a given port. Similarly, if we connect a voltage source across one port of a given S-parameter and a DC current source across another port, we will not be able to isolate the resistance due to a given net. The resistance represented as the voltage difference across the port connected to the current source will always include the effects from the reference net.

With a port-based package model, the choice of the reference node(s) at the die side imposes a tradeoff between accuracy and resolution. If the reference nodes are coarsely grouped around a power bump, then a more realistic and shared return path is modeled—but the voltage variation across these reference bumps is no longer considered. If the reference nodes are finely grouped around a power bump, then a more pessimistic and constrained return path is modeled and the reference net will have a larger parasitic effect than reality. While it may be possible to find a grouping of reference bumps that does a reasonable job of modeling the return path for a given power bump at the center of the a group, the modeling of the return path for the bumps at the periphery of the reference group will not be realistic.

The use of terminal-based RLCK physical models of the package removes such ambiguity.

Case for Unified Chip-Package Analyses
Today’s SoCs have a large number of distinct power and ground supplies, each with hundreds of C4 bumps. Additionally a large number of possible activities can take place, changing the current profile significantly across the chip and over time. With so much variation in power density across the die it is important to be able to perform power integrity analysis over a larger number of conditions without increasing the design cycle. The growing need to analyze chip and package for power integrity in context of each other, as well as their unique conditions, increases the need to perform chip-package co-analysis in a timely manner. The most effective method for chip-package co-analysis is to bring both the package and the chip layouts into a same simulation platform. This gives immediate feedback regarding the impact of the on-chip current distribution—over time and over the chip’s area—on the package design, as well as the impact of the package parasitics on the chip’s performance.

A unified approach eliminates the tedious and error-prone process of connecting an externally created package model to a chip for chip-package analysis. It also tightens the communication loop between chip and the package designers by enabling the chip designer to understand the impact of their chip on the package and immediately providing that feedback to the package team. If the package and chip layouts can be analyzed within the same simulation platform then it is straight forward to drive this unified methodology.

Using an RLCK package model with high-bump resolution will be more prevalent as SoCs increasingly become more complex systems. It will continue to be the case that with such complex distributions of power density and supply networks. Both the package and the chip will need to be analyzed in the context of each other for a large number of conditions. Having the package and chip layouts associated with each other in the same simulation platform will help improve efficiency and enable chip-package convergence.