How to improve verification.
Across the board, when I talk with people about power management verification or any verification actually, the topic of quality always comes up.
The first plan of attack is to look at coverage: how it is managed, how to perform coverage in a more constructed way. Ellie Burns at Mentor Graphics mentioned that because UPF can define all of the states of the system, the states of the power management, the control signals, etc., many engineering teams find it is ideal to raise the level of verification quality by developing a coverage plan that includes all of the power management architecture.
She observed that this is becoming more important because of new power management controllers for SoCs being developed. And here it is critical to understand that all of the states and transitions are verified very carefully.
This especially important to get handle on today as more and more power management is added to designs because the mere practice of adding the power management can break clock domain crossings. Fortunately, formal verification can be applied to figure out where those things are broken and provide fixes for them.
Another common practice that seems to go against logic is the tradition of waiting until late in the design cycle to begin power verification. Apparently, there are still many engineering teams waiting until the full SoC stage, and that is causing tremendous verification challenges because of the complexity of so much of the power control. Just as in the full SoC, the same attention must be paid to the IP and individual blocks and subsystems. You just can’t wait until the very end with such complexity, Burns added.
In essence, there needs to be a move away from looking at power from a physical perspective, and taking a more logical approach to it.
What are your thoughts on this? Please share your thoughts below.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply