The Next Big Leap: Energy Optimization

The relationship between power and energy is technically simple, but its implication on the EDA flow is enormous. There are no tools or flows today that allow you to analyze, implement, and optimize a design for energy consumption, and getting to that point will require a paradigm shift within the semiconductor industry. The industry talks a lot about power, and power may have become a more ... » read more

Static Verification Of Low Power Designs

Are there any chips designed today that don’t have limitations on their power consumption? For smartphones and tablets, increasing the time between charges is a clear product differentiator and a frequent design goal. Power consumption is also an issue for Internet-of-Things (IoT) devices, many of which are in inaccessible locations where battery replacement or recharge is difficult. Even com... » read more

Does Power Verification Work?

Functional verification continues to evolve, but power verification—a somewhat new concern—remains at levels of sophistication reminiscent of functional verification 30 years ago. When will power verification catch up and what must to happen to make it possible? These are questions that the industry is still grappling with, and not everyone believes they require answers. Functional error... » read more

Divide And Conquer: A Power Verification Methodology Approach

It’s no secret that the power verification challenge has grown by leaps and bounds in the recent past, especially considering design complexity and the sharp rise in the number of power domains in an SoC. As a result, SoC teams want to apply a rigorous [getkc id="10" kc_name="Verification"] flow, observed Gabriel Chidolue, verification technologist at [getentity id="22017" e_name="Mentor G... » read more

Verification Quality Comes Into Focus

Across the board, when I talk with people about power management verification or any verification actually, the topic of quality always comes up. The first plan of attack is to look at coverage: how it is managed, how to perform coverage in a more constructed way. Ellie Burns at Mentor Graphics mentioned that because UPF can define all of the states of the system, the states of the power man... » read more

Power Verification Now Required

Today’s verification tasks may seem daunting — and much of it is — but all of it is absolutely necessary to make sure chips operate properly with a larger system. Throw power into the mix and the challenges mount. The good news is that there is no shortage of tools and methodologies to help with these tasks. The bad news is that even the best tools won’t make the challenges disappear... » read more