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Static Verification Of Low Power Designs

The stages of a modern low power development and verification flow.

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Are there any chips designed today that don’t have limitations on their power consumption? For smartphones and tablets, increasing the time between charges is a clear product differentiator and a frequent design goal. Power consumption is also an issue for Internet-of-Things (IoT) devices, many of which are in inaccessible locations where battery replacement or recharge is difficult. Even compute servers and networking hardware face power limitations; the cost of electricity over their lifetime may be more than the initial outlay. The result is that virtually all chip designers face low power challenges.

In response, the electronics industry has developed techniques to reduce and manage power. Many of these involve slowing or shutting off entirely portions of the chip not currently required. The usual goal is to run the chip fast enough to satisfy critical application requirements while keeping power consumption within acceptable limits. Just as with any other functionality, power-related features must be fully verified before the chip is built. Failure to do so can easily result in a device that locks up or suffers thermal breakdown due to excessive power draw.

Many low power design techniques are amenable to partial automation during the development process. Special state-retention elements can be added to keep a minimal amount of power available to registers whose contents must be preserved during power shutdowns. A tool can insert isolation cells on signals coming from regions that are turned off and add level shifters to signals crossing between regions with different voltages and different switching thresholds. To avoid misunderstandings, it is best if designers, verification engineers and development tools share a common, unambiguous representation of low power design intent.

The Accellera standards organization provided the solution by defining the Unified Power Format (UPF) and donating it to the Institute of Electrical and Electronics Engineers (IEEE). The latest release is IEEE 1801-2015, IEEE Standard for Design and Verification of Low Power Integrated Circuits. A UPF file defines the areas of the design whose power can be controlled (power domains), the allowed combinations of power domains on and off (power states) and the signals that control power. It also specifies memory retention strategies, isolation cells, level shifters, and power/ground pins. Both hardware designers and automated tools in the development flow add power-related elements to match the UPF specification.

All aspects of low power design must be verified statically, and this should happen in four stages: the UPF file itself, UPF against the register-transfer level (RTL) design, UPF against the post-synthesis netlist and UPF against the post-place-and-route power-ground (PG) netlist. Since the entire low power design and verification process leverages the UPF description, it should be checked for errors as soon as it is written. Syntax, semantics and internal consistency can be verified early in the development process, even before RTL is available.

The second stage entails checking UPF against the RTL. It is common for different engineers to create the UPF description and the RTL implementation. Even when a single designer is responsible for both, it is easy for the UPF file to become outdated as the design evolves. Checks should be run any time either the power intent or RTL changes, ensuring that they remain in sync. Many types of errors can be detected at this stage, including missing or unspecified power domains and power control signals.

In a modern low power development flow, the logic synthesis tool reads in the UPF file and automatically inserts many power control structures into the design. These include isolation cells, level shifters, retention registers and always-on cells. The synthesis tool should generate a modified UPF file (UPF’) reflecting the structures inserted. The third stage of the static low-power verification flow checks the post-synthesis netlist against the UPF’ file, verifying the insertion and connection of all the structures. This process reveals any errors in the UPF, improper synthesis directives, or issues with the synthesis flow itself.

Low power automation continues as the place and route tool reads in the UPF’ file and inserts additional power control structures, including power switches, into the design. It should generate a UPF’’ file reflecting these additions. The final stage of low power verification repeats the checks from the previous stage to ensure that the place-and-route process has not introduced new issues. Additional structural checks verify the power switches, while power and ground checks verify that all aspects of power control are correct in the full PG-connected design.

As shown in Figure 1, Synopsys provides a static low-power verification flow spanning all four stages. The heart of the flow is the VC LP static low power verification solution. Both logic synthesis with Synopsys Design Compiler and place-and-route with Synopsys IC Compiler II read in a UPF file, use its information to add low power support to the design and write out a modified UPF description updated to reflect the additions. VC LP performs checks on the UPF files and verifies them against the design representations. The static flow leverages special features within the Synopsys Spyglass Power tool to debug violations and is fully complementary to native low power simulation using Synopsys VCS NLP.


Figure 1: The Synopsys static low power verification flow includes four stages.

With rapid growth in the number of end applications concerned about power consumption, low power design techniques are important in most complex semiconductor designs. Many of these techniques are specified in a UPF power intent file complying with the IEEE 1801-2015 standard. Synopsys provides an unparalleled solution for static verification of low power designs that includes four stages from stand-alone UPF file to the PG-netlist. Chip development teams can employ the most advanced power management techniques available with confidence that the design will operate properly in all power states. For a white paper with more technical detail, click here.



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