Power Management And Integration Of IPs In SoCs: Part 2


Most IP are available as either soft or hard macros. But both pose immense challenges. This is especially so when integrating them into low power designs and conducting power aware (PA) verification, because the majority of IP are self-contained and pre-verified at the block level and they must be preserved in their entirety when integrated or verified in the SoC level. Part one of this two ... » read more

Power Management And Integration Of IPs In SoCs: Part 1


IPs – whether in the form of soft or hard macros – are the epicenter of today’s SoC designs. Integration of IP with low power designs and conducting power aware (PA) verification are always complex and cumbersome. Because most of these IPs are self-contained, pre-verified at the block level, and must be preserved in their totality when integrated or verified at the SoC level. Until UPF... » read more

Static Verification Of Low Power Designs


Are there any chips designed today that don’t have limitations on their power consumption? For smartphones and tablets, increasing the time between charges is a clear product differentiator and a frequent design goal. Power consumption is also an issue for Internet-of-Things (IoT) devices, many of which are in inaccessible locations where battery replacement or recharge is difficult. Even com... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification


By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

I Say ‘High’ [Performance], You Say ‘Low’ [Power]


“…You say ‘why’, and I say ‘I don’t know…’” Actually, I do know. Everybody loves a high-performance product. Even just hearing that a product is high-performance sets higher expectations than if the product is simply described as “fast” or “powerful.” When it comes to SoC design, “high-performance” refers to a set of designs that run at very high clock freque... » read more

Could DVCon Be Better?


DVCon is undoubtedly the best conference in the industry if your interest is functional verification. In the past, it has also had a slant toward design. The focus is quite simply based on the standards activity going on within [getentity id="22028" e_name="Accellera"], the EDA industry's body that turns problems into solution in a short space of time. As those standards mature, they are handed... » read more

Mixed-Signal Design Powers Ahead


Mixed-signal devices are at the heart of many advanced systems today because of the need to interact with the outside world, but designing and verifying these systems is getting harder. There are several reasons for this. First, almost all of these devices now have to be lower power than in the past, and in the analog space it's not as simple as just dialing down part of a block. Second, it ... » read more

A Tale Of Two Standards


By Ed Sperling It could well be one of the strangest developments in standards history. Two competing standards for power formats were rolled out in the middle of the last decade and aside from a few cries of foul they fell below the radar screen of most chip designers and architects for a half-dozen years. Fast forward to the present and the Common Power Format (CPF) and Unified Power Form... » read more

Experts At The Table: The Trouble With Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Verifying Your Intent


Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

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