Video Compression Enables Cutting-Edge Displays

Transporting an increasing number of pixels over current display interfaces without compromising quality.


Display technology has advanced in leaps and bounds. We can now create professional-quality video content on our mobiles, and our cars often have more displays than our living room. In recent years, electronics manufacturers have been using increasingly sophisticated display feature sets as a way of differentiating their products in the highly competitive consumer electronics market. Each new generation of products pushes the boundaries of display technology even further with higher resolutions, faster refresh rates, and increased pixel depth at the forefront of these developments.

What end users do not see behind the scenes is the incredible number of pixels that make up these innovative displays. Whether it is a mobile, augmented and virtual reality (AR/VR), or automotive display, an application processor (AP) generates pixels, which are then transported over a physical interface (PHY) to the display. As display resolutions have increased, so has the amount of pixel data transferred over the PHY. This leaves designers with the tough task of finding ways to transport all these pixels over current display interfaces, without compromising on cost, power consumption, and, most importantly, visual quality.

Between 2010 and 2020, display resolution in mobile phones went from HD (1280×720) to 4K (3840×2160); this represents a growth of 23X in display bandwidth requirements from 1.3 gigabits per second (Gbps) to 29.9 Gbps! Across the mobile, augmented and virtual reality (AR/VR), and automotive markets, display bandwidth usage has been growing by approximately 40% per year, while the bandwidth of the available display physical (PHY) interfaces has increased at half that rate. There are few ways to close this gap between the two; designers can either increase the number of physical data lanes in their design, which in turn has a knock-on effect on cost and power consumption, or use video compression to reduce the total bandwidth requirements.

Having recognized the need for video compression on display interfaces, the Video Electronics Standards Association (VESA) first initiated efforts for a common, industry-wide standard in 2012. What followed in 2014 was the release of VESA Display Stream Compression (DSC), the industry’s first visually lossless video compression codec. The MIPI Alliance was the first organization to adopt the use of DSC inside its transport standard, MIPI Display Serial Interface (DSI). While initially designed for mobile devices, VESA DSC was widely adopted in other display-based products including AR/VR headsets, cars, TVs, monitors, and GPUs (graphics processing units).

As display bandwidth requirements kept growing, VESA identified the need for a second compression codec that would offer additional compression capabilities, while offering the same visually lossless picture quality. VDC-M (VESA Display Compression) was announced in 2018 and MIPI Alliance was again the first organization to adopt VDC-M into their transport standard, MIPI Display Serial Interface 2 (DSI-2).

Both codecs are visually lossless, meaning that the end user cannot distinguish between the uncompressed original images and the compressed version. This has been proven through a series of rigorous tests conducted by VESA. Since the codecs are used across a wide range of applications, the algorithms have been designed to render excellent quality across all types of content including images and video, text, graphics, and even complex engineering test patterns!

DSC can compress any uncompressed image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image. VDC-M uses a set of more sophisticated video encoding tools to achieve even higher compression factors, all while offering the same or even better picture quality. For example, it can reduce a 30 bpp uncompressed image to 6 bpp, and in some use cases, it can be visually lossless at a 6X compression ratio.

You might be wondering at this point how designers should choose between DSC and VDC-M? It really depends on the bandwidth, power requirements, and interoperability requirements of each application. As is always the case, there is also a trade-off between compression capabilities and the codec complexity. While you can hit those higher compression ratios with VDC-M, the codec is larger in terms of gate count and RAM (Random Access Memory) usage due to the more complex algorithms that it uses. It is expected that both compression codecs will co-exist for the near future with designers opting for VDC-M when they need to support extremely high resolutions, pixel depths, and frame rates.

Originally developed by Hardent, Rambus offers both encoder and decoder IP cores supporting the VESA DSC and VESA VDC-M compression standards. These IP cores are silicon proven, with 100+ design wins using DSC and VDC-M, including major application processor and DDIC (Display Driver Integrated Circuit) vendors. In addition, Rambus also offers a fully integrated, off-the-shelf display IP subsystem solution, consisting of Rambus (MIPI DSI-2 controller), Hardent (VESA DSC), Mixel (MIPI C-PHY/D-PHY combo) IP to facilitate the integration of video compression across a range of display applications.

Additional resource:
Rambus DSC & VDC-M IP Cores

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