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Why Every Design IP Needs A Complete QA Methodology

Catching IP correctness problems early in the design flow.

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Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables modularization and re-use of design components, so that designers can leverage already-existing components as a baseline to accelerate design schedules. Therefore, it is not surprising that the usage of design IP has grown rapidly in the past decade.

However, like any component of a silicon design, IP may contain errors which are difficult to detect due to the vast number of views and values contained in an IP library. This article explains how Solido Crosscheck can verify the correctness of the design IPs effectively and catch problems early in the design flow.

The importance of having a robust QA methodology

Since design IP are the building blocks of modern IC design, one of the most important metrics for IP, aside from functionality and power/performance/area (PPA), is the quality of the IP from a QA standpoint.

Fig. 1: The different design views and formats used in IP production and integration flows.

Design IPs that have passed robust QA are easier to integrate, result in better silicon results, and help shorten production schedules. This is because a proper QA methodology ensures design IPs have the following QA metrics:

  • Correct and consistent encapsulation of IP information: Different design views and formats such as physical, timing, electrical, and other views are correct and align with each other.
  • Tool-agnostic IP usability: The IP is agnostic to the integration tool. E.g., IP that works well with any toolset regardless of EDA flow or mixed-vendor flows.
  • IP performance and specs that are consistent with datasheets and documentation: Integration teams can rely on datasheets and other documentation to make decisions on IP usage

Let’s take a closer look at these qualities and why they are important:

Correct and consistent encapsulation of IP information

Integration tools such synthesis, place-and-route, or digital/analog-on-top environments require input library and IP information to be correct and consistent, to properly perform design closure or final integration. Errors in design IP may lead to additional schedule time and engineering time for design closure, or expensive engineering change orders (ECOs) and re-spins.

These errors may include differences in cell or pin names, missing layout views, or even more subtle issues such as mismatched metal layers, or inconsistent cell/IP block sizes across different design formats. While some issues can be caught by P&R tools or analog integration environments, many issues may remain undiscovered, causing expensive issues later in the design flow.

Because of this, IP integration teams such as chip level design, implementation, and verification teams will typically run incoming IP inspection on all components of their design. However, since these teams manage many different IPs, including standard cells, embedded SRAMs, and custom IP blocks, it quickly becomes a resource-intensive task to weed out inconsistencies or other errors in design IP if these issues arise in multiple places.

Working with well-tested IPs that are correct and consistent across design views allows for easier integration and a more predictable production schedule and is a notable factor for consideration when selecting IPs for a project.

Tool-agnostic IP usability

Different IP integration teams use different toolsets, and many integration teams have methodologies comprised of mixed-vendor toolsets.

As an IP provider, ensuring IP usability across tool flows expands the potential user base and reach of that IP, allowing more teams to benefit from including the IP in their chip-level designs. Therefore, wherever possible, IP QA should not be restricted to only target a subset of tools.

However, this is easier said than done, since EDA tools tend to have different standards on what is considered acceptable input data. For some tools, the ability to auto-fix or calibrate for common issues in input data is seen as an advantage, especially to push through prototyping or implementation stages.

For an IP to be broadly usable across different EDA toolsets, a robust IP QA methodology should check for adherence to specifications (such as .lib, LEF, GDS2, SPICE, etc.) that are unaffected by “shortcuts” of convenience taken by a subset of integration tools.

IP performance and specs that are consistent with datasheets and documentation

Datasheets and documentation are an integral part of design IPs and are often considered one of the design views for IPs. Clear, concise, and accurate datasheets not only help shorten IP integration time, but also provide useful insight into whether an IP is a good fit for the target application.

In addition, for each revision made to the design IP, performance and specs may change either intentionally (e.g., targeted overall power improvement of the IP), or as a side effect of changes (e.g., timing or power differences from layout modifications).

Therefore, a QA methodology must be able to validate that IP properties are aligned with datasheet and other documentation, and provide the necessary information to update the documentation, or identify what needs to be fixed in the IP when discrepancies are detected. This ensures that IP integration teams obtain the correct information to make design decisions when using the IP.

Setting up comprehensive, repeatable, and scalable IP QA

Solido Crosscheck provides a comprehensive IP QA framework that works for all IP types. It is an independent, tool-agnostic QA solution for design IP data, and can understand and evaluate the many design views and formats used in IP production and integration flows. It is also customizable with APIs to enable custom checks and reports.

Fig. 2: Solido Crosscheck IP QA Framework.

Using Solido Crosscheck, design teams can ensure IP is correct, robust, and easily integrated into top-level designs, resulting in faster design and verification cycles at the chip level.

For more information, check out Solido Crosscheck here.



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