Verification reuse; highly paid engineers; M stuff; logos; simpler times; analog PDKs; papers; undersinks; package rules.
By Ed Sperling
Mentor’s Harry Foster rolls out part four of his epic functional verification study, this one on design and verification reuse. If you work in the verification world, pounce.
Cadence’s Brian Fuller looks back over a quarter century of technology—and what the average salary of a hardware design engineer will be in a 15 years: $499,000. But what will a cup of coffee cost?
Synopsys’ Scott Knowlton digs into M-PCIe with M-PHY, including what it is and why it’s important for power and performance.
Dassault SolidWorks’ John Lam gives a brief tutorial about how to replace an uninteresting Viewport compass with something much more interesting, such as your company’s logo.
Mentor’s Colin Walls looks backward to a simpler time, when at least code writers didn’t have to worry about power. Simpler, maybe, but it was never actually easy.
Cadence’s Richard Goering shines a spotlight on a custom/analog deal with TSMC. The foundry will provide SKILL-based PDKs for its 16nm finFET process. TSMC also is upping its use of Cadence’s Virtuoso to design its own IP.
Synopsys’ Mick Posner points to a paper from Broadcom’s Paul Robertson and Synopsys’ Andy Jolley about complex SoC prototyping using an FPGA protyping board. The paper won a “Best of SNUG” award.
Mentor’s Robin Bornoff digs into heat flow paths, undersinking, pads and vias in part three of his thermal analysis study.
Cadence’s Team Allegro looks at how to confidently tweak IC package design rules. There’s a video tutorial to go with it.
 |
 |
 |
 |
 |
 |
 |
 |
 |  |
Leave a Reply