2.5D Leverages Existing Tools On The Way To 3D

By Ann Steffora Mutschler
As design and manufacturing issues with true 3D design continue to be worked out, interim 2.5D technologies are moving ahead as engineering teams leverage this packaging-driven approach to manage heat, cost, area and yield.

Technologies such as Wide I/O memory support 2.5D, and when combined with logic they allow engineering teams to realize a performance increase, particularly for applications such as GPUs and gaming where there aren’t significant area constraints but there are performance and power demands.

“That’s where people are using Wide I/O memory and logic side by side in a 2.5D silicon interposer configuration,” observed Samta Bansal, senior product marketing manager for Silicon Realization at Cadence. Also, there is less of a heat management burden for 2.5D—another reason that engineering teams are looking at 2.5D now.

On the power side of 2.5D designs there are some extra issues that have to be considered during the design process, pointed out Steve Smith, senior director of 3D IC strategy and marketing at Synopsys. “For example, the die that you place on the interposer are bare die. They are not packaged. This is one of the issues that you have to think about. How do you drive the signal connections between each die which are relatively long? You could have relatively long wires feeding between a pair of die—maybe like in the case of Xilinx they talk about actually building special I/O drivers that are matched according to the power needed to drive the signal across a certain length of wire. They figured out based on the length of wire how big the drive strength should be and then modeled that and created a special I/O cell.”

Another power issue with 2.5D is how to get power reliably into the die from the interposer, he said. “The way it works with a silicon interposer is the power comes from outside of the package all the way back to the battery, basically up through the package I/O, up through the interposer through silicon vias (the metal connections from the front to the back of the interposer die) and then gets transferred up into the die themselves so the actual TSVs, the placement of them, the number of them have to be figured out to reliably get enough power up to the die. Then you also have to think in terms of the signals that cross between the die and make sure you have enough power to drive those as well.”

Thermally speaking, there are heat issues with 2.5D-stacked designs, but these are being modeled with traditional thermal tools that engineering teams are already using.

“At the moment, we’ve got an interposer and essentially flip chips sitting on top of them, so a lot of the modeling is happening at a macro level using traditional tools and current systems. I think it will start to change when we convert those simple flip chips—simple being a relative term—to being a true, active die that has through silicon vias in it, and then where it’s stacking multiple things up higher in there. I think that’s when we’ll see the next fracture of the methodologies,” noted Matthew Hogan, Calibre marketing engineer in the Design-to-Silicon division at Mentor Graphics.

Some challenges not technology-related
In addition to the thermal and power issues, there are also challenges related to how to best allocate the new tasks inherent in 2.5D design.

“Traditionally in the IC realm a lot of organizations are set up with a system architect that designs the chip and the chip gets broken up into little blocks. The teams then go away for 3 to 18 months, then come back and do final chip assembly,” Hogan said. “All of those jobs and tasks are very well identified and we have the tradition of who does what, where and when. Eventually we go into the package side of things. One of the things that we’re seeing is from a 2.5D and 3D IC perspective, we now have this concept that gets overlaid where we’ve got a system netlist, so it’s a system design where we’ve got our flip chips on top with our interposer.

But who actually owns the netlist isn’t always clear.

“If you take a traditional IC design flow then maybe you’d say the packaging guys did the assembly and the package and that sort of stuff—maybe it’s over there. If you have a look at the front of this whole system, you’ve got a system architect working in ESL and he doesn’t necessarily deal with the 128-bit data bus that’s got level shifting on it. He deals with, ‘I need a communication channel between this chip and that chip that does 3.5Mbps because this is the data stream that I want.’ Somewhere within the definition of the high-level architectural view of what the system needs to look like and the physical implementation there really needs to be ownership of this system netlist, which is a pin-accurate description of how these different devices and designs are going to be connected together. That’s what you use when you go and do your verification of the complete 3D assembly,” he said.

The result is that ‘traditional’ IC design and verification groups need to expand and look for either different resources or tweak what they consider their roles and responsibilities so they can handle this new system netlist. That way, when they verify the 2.5D or 3D stack they understand who owns what, where it comes from and how it was created.

“They’re doing these sorts of netlists already when they do their LVS verification and there’s a golden LVS netlist,” Hogan said. “But that guy’s dealing with one chip and a whole bunch of IP internally when you get out to the system of 2.5 and 3D stacks. It’s that system view that you need to create yet again—another golden system netlist.”

Are new tools required for 2.5D?
With any new technology, there is always a concern in the minds of engineers about whether they will have to add new tools to take advantage of what the new technology offers. With 2.5D, engineers can rest easy, for the most part.

Generally design teams are able to use a lot of the traditional techniques and tools that they’re currently using to really understand what’s happening from a power and thermal perspective in 2.5D.

Synopsys’ Smith pointed to the oft-quoted Xilinx stacking example and noted, “They’re claiming they started working on their interposer design eight years ago. At that time, there were no special tools for doing this, although strictly speaking you could regard 2.5D as kind of like a multi-chip module, which has been around for decades. It’s a packaging concept where you put different die on a package substrate like a mini circuit board. So that’s been there.”

Replacing package substrates with a silicon interposer results in the same kinds of issues, he noted. “You’ve got the close proximity of the die, they’re all going to be packaged together in the same package, so I think the thermal issues, for example, are very similar in that sense. I think the reason why companies are saying they’re managing is because this is very familiar to them. The people that work in the IC design companies usually have a separate packaging group/team from the design team, so the packaging team would be the ones that have the expertise in dealing with thermal issues with multiple die in a package. The advantage of an interposers is, because we’re not stacking active dies on top of one another there are no issues with die interfering directly with each other. If you did a true 3D IC, you’d be stacking active die on top of one another. Then you have a massive thermal issue.”

In 2.5D, the interposer has no transistors on it. It’s just wiring. And the tools that are used for thermal analysis of packages are equally applicable to 2.5D. While it is a rough analysis (because that’s all that’s needed for now), in 3D IC design the analysis is more complex because the areas in the silicon die with the higher temperatures must be identified as this impacts performance.

All of the big EDA vendors began addressing 3D design issues a few years ago and are well on their way. When the industry changed focus to 2.5D as an interim step driven by the foundries and packaging companies, the most complex issues were already identified.

From Synopsys’ perspective, the most dramatic impact to the 2D design flow to accommodate 2.5D has been the routing for the interposer, so the company added a more regular silicon routing system. At Cadence, Bansal noted that the company has been building up its 2.5D/3D flow most notably with STMicroelectronics; in addition to its inclusion in foundry reference flows. Mentor, as well, has extended a number of its tools to accommodate 2.5D/3D IC design and has established key relationships with foundries such as inclusion in reference flows.

At the end of the day, engineering teams can leverage the benefits of 2.5D now using existing tools as they prepare their organization and methodologies for the full step to 3D when the time comes.