March 2009


New Tools, New Economics


The race is on to get new development tools out the door, and starting next month you’ll begin seeing many more of them.   Timing is everything, and these tools have to be ready for the next round of chip development—even if the chips aren’t being designed yet. But given that electronics design has to precede an industry recovery by 6 to 12 months, at the very least, and chips and ot... » read more

Easing System Creation With Embedded Hardware Solutions And Standards


By Cheryl Ajluni System creation is today an ultra-complex task. On one hand, developers are confronted with consumer demands for ever more functionality, better performance and increased power efficiency at a lower cost. On the other hand, they face stringent time-to-market requirements and changing standards, coupled with the need to accommodate a range of requirements pertaining to differen... » read more

Exclusive Research: What’s Happening With Third-Party IP


Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP. While it’s too early to tell this year what effect that will have on overall design activity—the economy is the rea... » read more

Taming The Multicore Beast


By Ed Sperling Multicore chips are here to stay. Now what? That question is echoing up and down the ranks of tools vendors, design engineers, software developers and even among people who measure the performance and efficiency of semiconductors. There is now a Multicore Expo and a Multicore Association that includes a who’s who of electronics. And there are lots of working groups developing... » read more

Thinking Digital To Design Analog, And Vice Versa


By Ed Sperling Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome. Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with is... » read more

Exploring The Use Of Virtual Platforms At The Electronic System Level


By Cheryl Ajluni System design is hard. That should not come as a surprise to anyone these days. With design geometries shrinking and device complexity on the rise, this fact is not likely to change anytime soon. One concept for easing that burden for system-level designers is the virtual platform. Granted, the concept itself is nothing new, but today it is being employed in ever more creativ... » read more

Trends in System-Level Prototyping


By Clive Maxfield One problem with electronics is that certain terms can mean different things, depending on who one is talking to at the time. Even worse, some terms have a tendency to evolve over time. This means that when we are presented with a topic like "Trends in System-Level Prototyping," before leaping headfirst into the fray, it may be a good idea to first define exactly what we mean... » read more

Why bother with ESL?


I’m in southern California today at the EDA Tech Form. I’ve been thinking about a conversation I had recently with a colleague. He’s been doing system-level modeling for a few years and has been an advocate for transaction-level modeling and ESL in his company. He has had tremendous success in identifying and fixing system-architecture issues before implementation, as well as saving his ... » read more

Everything Changes At 45nm


Design engineers are pretty good about sharing ideas with their colleagues. They’re extremely good about sharing the limelight with their peers. But they’re not particularly good about implementing new ideas and concepts and changing the way they work.   There are good reasons for this, of course. It takes a long time to become proficient at skills for designing new chips or creating a... » read more

Follow The Design Activity


Everyone seems to be on a low-power kick, from the ASIC/ASSP world to the growing market of low-power embedded processors and SoCs. But what do the actual numbers tell us about the future trends for such low-power designs? One way to answer that question is to look at the result of architectural tradeoff studies currently being performed by chip designers. (See chart below) A causal glance a... » read more

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