Everything Changes At 45nm

Design engineers are pretty good about sharing ideas with their colleagues. They’re extremely good about sharing the limelight with their peers. But they’re not particularly good about implementing new ideas and concepts and changing the way they work.

There are good reasons for this, of course. It takes a long time to become proficient at skills for designing new chips or creating architectures, and no one has enough time these days to fool around with new ways of doing things. And up until 90nm, the buzz about things like design for manufacturing, transaction-level modeling, and even automated analog design were relegated to the marketing departments.

At 65nm, DFM became a necessity. At 45nm, so will ESL. And at 32nm and beyond, all of this will be combined with vertical stacking, new substrates and other materials, new gate structures, and more integration of software and hardware, multiple power islands and complex timing. In this scenario, the most highly valued attribute for engineers will be understanding as many pieces of the chip design as possible, rather than just being an expert in one area, and at least understanding how to integrate everything from third-party IP to developing software prototypes and interconnects.

This is complex stuff, and no one has the ability to learn everything. But everyone who wants to have a place in overseeing design will at least have to understand the concepts and speak the language of integration. We are at a point where complexity is forcing economic changes—it takes more money to develop chips, it takes more volume to make them successful, and it takes more money to engineer products out the door in shrinking market windows. Those economic changes already are starting to boomerang back to the design world, and ultimately they will have a profound impact on individual engineers.

In the midst of all of this, learning new things may seem like the last thing an engineer should be doing. It may not even pay off for a couple years. But by the time the industry hits 45nm as a volume platform, and 32nm on the most advanced nodes, rewards will go to those who understand new concepts, new approaches and how to integrate everything together.

The clock is ticking.

–Ed Sperling