May 2009

EUV Is Late—And It Hurts

Most chip architects and engineers couldn’t give a whit about the difference between deep ultraviolet and extreme ultraviolet lithography. It’s traditionally been a problem that foundries had to wrestle with, and that was their problem. Even DFM has been slow to catch on because what’s done in a foundry is of little interest up front.   The separation of those two worlds worked fine ... » read more

Hiring Begins Again—Slowly

By Ann Mutschler & Ed Sperling After one of the longest downturns in many decades, hiring has started again in parts of the semiconductor industry. No one would call it a hiring boom, and some companies that have been postponing layoffs are still making cuts, but there is definitely is a change under way. This is evident on some of the job boards, which have postings for engineers with pa... » read more

Problems In Multicore Design

Jon McDonald talks about the multitude of choices in multicore design and what to do about it. Click here to watch the video. » read more

Why Semiconductor Packaging Matters

By Ann Steffora Mutschler After decades of being considered almost an afterthought, semiconductor packaging is emerging as an integral part of the Moore’s Law road map. Power, heat, manufacturing and impurities like soft errors have become so pronounced at 45nm and 32nm that they are actually beginning affect the package. And while these problems are not new, continual shrinking has made th... » read more

Pain Points At 22nm And Beyond

By Ed Sperling The roadmap for 22nm has a giant pothole in the middle of it. That hole is supposed to be filled by extreme ultraviolet lithography, or EUV. Instead it is being patched up using immersion lithography, which is about to cause some monumental headaches for design teams. The difference is comparable to a surgeon using a chainsaw instead of a scalpel. The cut isn’t nearly as ... » read more

Formal Verification 101

By Clive "Max" Maxfield The first time I came into contact with the concepts of a digital hardware description language (HDL) and digital logic simulation, I inherently understood how it all "worked." The idea that the statements in the modeling language acted in a concurrent manner just seemed to make sense. By comparison, trying to wrap my brain around formal verification has always mad... » read more

Where SaaS Works Best

By Ed Sperling Some of the largest corporations in the world use software-as-a-service, or SaaS to run their enterprise applications, trusting day-to-day operations to companies like, Oracle, Microsoft and even Google. But good luck finding any leading-edge chip vendors utilizing the SaaS model for their designs. While Cadence has been successful with some of its low-end to... » read more

Making Sense Out Of Convergence

By Ed Sperling Technology convergence and market consolidation have always gone hand in hand, although not necessarily in ways everyone expects. The confluence of video and audio was first exhibited by AT&T at the 1964 World’s Fair. The rather crude videophone demonstration promised a future where people could actually see the person they were talking with. Fast forward 45 years and... » read more

What Else Needs To Change

Rising complexity at each new node may require a different skill set for design engineers in the future. What exactly needs to be included in that skill set remains open to debate, and it probably will continue to evolve. But there are some clear trends emerging.   First of all, there’s the software. While software engineers can write code, hardware engineers who understand programming c... » read more

The Next Problem In Verification

Last week’s blog on OVM vs. VMM was like a match on dry timber, which is probably a bad analogy to make in California these days. Weeding through the comments—both on the record and off, and there was plenty more off the record—it appears there’s plenty of work under way to bridge the two worlds, but there’s an inverse amount of information available to the people who use one or the... » read more

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