June 2010 - Semiconductor Engineering

Experts At The Table: Nice To Have Vs. Need To Have
By Ed Sperling - 25 Jun, 2010 - Comments: 0

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation. LPE... » read more

End User Report: EDA Industry Realignment
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, ... » read more

Design For Variability
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling Faced with shrinking margins, manufacturing process fluctuations that could mean one more or one less atom in a transistor and proximity issues in layout the most advanced chipmakers have begun designing for variability. Rather than working with fixed numbers, such as voltage, power and area, the goal of DFV is basically averaging all of these numbers. While this includes som... » read more

Connecting The Pieces
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qual... » read more

AMS Reference Flow 1.0: Ready For Prime Time?
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Pallab Chatterjee TSMC recently announced a game-changing flow for 32nm/28nm Analog Mixed Signal (AMS) design. The AMS flow 1.0 includes tools from multiple vendors that are sequenced to take a design from concept and device creation all the way to release to being included as IP in an SoC. The flow that is being offered is a departure from traditional custom analog and custom AMS design. ... » read more

Stressing Over 3D
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

The Future Of IP
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP. In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exac... » read more

Redefining ‘Good Enough’
By Ed Sperling - 24 Jun, 2010 - Comments: 0

The increasing amount of software content in devices and the ability to add fixes after tapeout is changing the definition of what’s considered a market-ready product. This is business as usual in the software world, where patches upon patches are considered routine. Service packs are a way of fixing problems when millions of lines of code interact with millions more lines of code in unan... » read more

Synopsys Plus Virage: Combinatorics Or Common Sense?
By Jack Harding - 24 Jun, 2010 - Comments: 0

By Jack Harding It should be no surprise. The industry has been consolidating and expanding and consolidating for nearly 40 years. So when Virage Logic was gobbled up by Synopsys and Denali was ingested by Cadence, it is really a lot more of the same. Or is it? There is a difference. Synopsys has made it crystal clear that its definition of EDA now permanently includes IP. Not that acquirin... » read more

The ‘Hospital Pass’ Of Chip Design
By Ron Craig - 24 Jun, 2010 - Comments: 0

By Ron Craig My wife is very understanding. Once every four years I become somehow distracted for 90 minute periods over the course of about a month, unresponsive to the most basic requests and occasionally straining to explain the minutiae of the offside trap, the beauty of the ‘nutmeg,’ the tactics of the three game group stage and why the flag didn’t go up because the left back on the... » read more

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