AMS Reference Flow 1.0: Ready For Prime Time?

The ambitious idea of a single flow for analog/mixed signal chips sounds great on paper, but don’t expect miracles.


By Pallab Chatterjee
TSMC recently announced a game-changing flow for 32nm/28nm Analog Mixed Signal (AMS) design. The AMS flow 1.0 includes tools from multiple vendors that are sequenced to take a design from concept and device creation all the way to release to being included as IP in an SoC. The flow that is being offered is a departure from traditional custom analog and custom AMS design.

Traditional custom design is made up of the following steps: circuit design (PDK-based), simulation (device-level, RF, fast simulation), layout (schematic-driven layout and polygon-level) and verification (DRC/LVS/DFM/LPE/fill, etc.) This flow has been in place since the late 1960s and is available from a number of EDA vendors on a single company or mix-and-match basis. To complete small designs (component level) these tools have been available for typically sub-$50,000/seat without the verification tools. The tool suite typically contains about five tools in the flow.

The new flow has the following high-level steps (see Fig. 1: circuit design, LDE (layout dependent effects) awareness and budgeting, schematic-driven layout and analog place and route, simulation, 3D extraction, yield and sensitivity analysis, noise analysis, IR/EM analysis and extraction. These new flows are a combination of many tools, most of which do not incorporate an interoperability standard for the stages.

The primary assumption is that the AMS flow is based on Open Access, which represents some levels of interoperability. However, it is far from complete. The tools needed to complete a midsize AMS design, once again not counting the core PV portion (DRC/LVS/fill/DFM) that is assumed to be already in place and of signoff quality, ranges from about $250,000 to $750,000 per seat based on vendor. With the SoC-level PV tools, it is typically more than $1 million per seat. (These prices are aggregated from the major EDA vendors list pricing for the full list of tools required.)

A typical implementation of an AMS flow from a single vendor is shown in the following figure provided by Magma. While the first impression is that the flow is very complete, all the necessary design information is not available in electronic form. Most of the LDE rules are guidelines, most of the RF and SI sensitivity information is qualitative rather than quantified, and the yield and manufacturability analysis are based only on fabrication, not design practices and functions or re-use models.

Most of the EDA vendors, while “endorsing” the flow, cannot actually support the automated creation of AMS designs using “Analog Synthesis Tools” the same way they’re done in digital. The design variability and the granularity (device level) of the AMS and IP creation realm is very company-specific and not easily generalized. Moreover, the assumption that simply by having a foundry declare a high-level sequence to follow exists will drive the EDA vendors to supply tools in cost-effective bundles for that market and suddenly gain design insight as to the best way to support the designs appears somewhat optimistic.

The avoidance by the EDA community to acknowledge the crucial role of the designer as something other than an operator is an issue because some tasks, especially those on cutting-edge processes and AMS design, do not have single overriding definitive solution for a design issue. This will result in a change in the support and license use models that have been the basis of the SoC flows to support AMS. The boutique community of IP, analog and AMS designers is skeptical of programmers providing design solutions based on data throughput and algorithmic elegance, but they are much more at home with historic design practices and principles.