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Virtuoso ADE Assembler


Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

AnastASICA — Towards Structured and Automated Analog/Mixed-Signal IC Design For Automotive Electronics


In our world based on electronics, the design of analog/mixed-signal (AMS) ICs is still mainly done manually. While digital design benefits from complete synthesis flows, analog lags far behind in terms of development time, cost, and risk. Analog design flows are hardly standardized and necessitate the four eye principle as important quality tool. Thus, highly experienced designers who incorpor... » read more

Re-Architecting SerDes


Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

From Constraints to Tape-Out: Towards a Continuous AMS Design Flow


Author(s): Krinke, Andreas; Horst, Tilman; Gläser, Georg; Grabmann, Martin; Markus, Tobias; Prautsch, Benjamin; Hatnik, Uwe; Lienig, Jens The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital... » read more

How To Speed Signoff Extraction By 5X With Next-Generation Extraction Tool


Parasitic extraction, particularly in the digital world, is becoming an increasingly time-consuming process. Not surprising, considering the explosion in interconnect corners, increasing design sizes and number of parasitics, and complex modeling features at advanced nodes, including FinFETs. This paper discusses capabilities you should have in order to overcome parasitic extraction challenges,... » read more

The Week In Review: Design


Tools Synopsys rolled out a major new release of its place and route tool, the centerpiece of its physical design platform, offering up to 10X improvement in speed—a combination of 5X faster implementation and 2X larger capacity. Co-CEO Aart de Geus called it the most significant product in the company’s history. Synopsys also rolled out an AMS verification platform to accelerate regres... » read more

Mentor Buys Berkeley Design


Mentor Graphics announced today that it has acquired Berkeley Design Automation, staking a claim on the expanding market for analog, mixed-signal and RF verification. The deal puts Mentor on firm footing against Synopsys and Cadence, just as the opportunity for the Internet of Things (IoT), including automotive and medical design, begins to show real promise. Until this move, Mentor has larg... » read more

Experts At The Table: The Future Of Verification


Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Cost vs. Value


By Ann Steffora Mutschler The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together. “... » read more

Reducing Circuitry To Reduce Power


By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

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