How To Speed Signoff Extraction By 5X With Next-Generation Extraction Tool

Tool Contributes to Faster Overall Design Closure

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Parasitic extraction, particularly in the digital world, is becoming an increasingly time-consuming process. Not surprising, considering the explosion in interconnect corners, increasing design sizes and number of parasitics, and complex modeling features at advanced nodes, including FinFETs. This paper discusses capabilities you should have in order to overcome parasitic extraction challenges, and introduces our next-generation extraction tool built on a proprietary massively parallel architecture that speeds signoff extraction turnaround time (TAT) up to 5X and provides best-in-class accuracy, as well as custom analog flows.

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