March 2011 - Page 3 of 5 - Semiconductor Engineering

Japan Quake Update
By Jim Feldhan - 18 Mar, 2011 - Comments: 0

By Jim Feldhan, Semico Research Nuclear Power Situation The damaged nuclear generating facilities continue to spiral out of control.  Not only are there three reactors damaged, now the spent fuel storage facilities are in serious trouble.  Similar to the reactors, the storage units need to be water-cooled.  The largest storage unit at the Daiichi Plant, containing 130 metric tons of n... » read more

Widening The Channels
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Wide I/O—both as a specific memory standard and as a generic approach for on-chip networking—has been looked at for the past couple of chip generations as a way of improving SoC performance. Increasingly, it also is being used as a key strategy for reducing energy consumption. Wide I/O refers to a number of different approaches in on-chip networking, ranging from through-... » read more

Power Panel: IP And Other Key Issues For Future Development
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Prapanna Tiwari: UPF and CPF are text files that capture the power i... » read more

Gene’s Law Meets EDA
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Pallab Chatterjee What will be the next major improvement that will cut power levels by an order of magnitude? That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law... » read more

The Shocking Side Of 3D
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler The pesky static charge that builds up on your clothing when you forget the dryer sheet is more than just a nuisance when it comes to manufacturing ICs. Add 3D structures and process scaling to the mix and the challenge of adequately protecting those devices grows significantly. While this problem used to be largely an afterthought, the charged-device model type of... » read more

The True Test Of IP Reuse
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler Fewer and fewer systems and semiconductor companies are designing brand new processors from scratch. Instead, they leverage as much IP as possible in their designs, investing selectivity in areas where they can add significant value. The challenges are varied from low-power issues to process technology migrations. Generally, IP consumers are doing two levels of IP-... » read more

Quicker Turnaround
By Aveek Sarkar - 17 Mar, 2011 - Comments: 0

By Aveek Sarkar Statistics indicate the increase in sales for mobile handsets in the emerging economies will be from the sale of smart phones. According to a Nielsen report, Brazilian sales of smart phones were up 128% in 2010, compared to 2009. These emerging economies have traditionally been served by standard cell phones that provided voice and texting needs (Fig. 1), but the consumers i... » read more

Core Power
By Barry Pangrle - 17 Mar, 2011 - Comments: 0

By Barry Pangrle What type of core should I choose if I want to be really power-efficient? That’s an interesting question. The answer that a lot of people will hate to hear is that it depends. Probably the first question that needs to be answered is, what does power-efficient mean to you and how power-efficient do you really want to be? Most people can’t wait forever for a result to be ... » read more

Fast LP Simulation
By Luke Lang - 17 Mar, 2011 - Comments: 0

By Luke Lang What are the most important features of a logic simulator? I’m sure there have been lots of surveys done for this question. Unfortunately, I can’t find any results on Google. Nevertheless, I would be willing to bet that fast performance is at or near the top of every verification engineer’s wish list. For the low-power verification engineers, fast performance is also a ke... » read more

Experts At The Table: Billion-Gate Design Challenges
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excer... » read more

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