The True Test Of IP Reuse

Not all IP is node and process independent; and even with some of the best designs it isn’t always easy.


By Ann Steffora Mutschler
Fewer and fewer systems and semiconductor companies are designing brand new processors from scratch. Instead, they leverage as much IP as possible in their designs, investing selectivity in areas where they can add significant value. The challenges are varied from low-power issues to process technology migrations.

Generally, IP consumers are doing two levels of IP-based reuse. First, they re-use fixed instruction set architecture (ISA) processors because by configuring and extending the instruction set they can make the base into something of their own. “They can add differentiation to it that you don’t get if you just license totally fixed processors from a totally fixed kind of processor company,” said Grant Martin, chief scientist at Tensilica.

Another level of IP-based reuse includes configuring and extending a processor because substantial reductions in energy consumption and peak power dissipation can be achieved if it can be tightly tuned to the application. “We can actually start by a processor type in a domain. I think audio processing is a really good illustration of how the application-specific nature to a processor allows you to get substantial reductions in energy consumption for very standard things like various kinds of audio codecs because the instructions you execute are so tuned to the application itself,” he said. “In many, many handheld and portable devices, people use programmable audio processors or ASIPs (application-specific instruction-set processors) that are highly tuned in that way. And it’s very few people who, as a result, would be tempted into designing their own unique hardware blocks for that function.”

MIPS has seen much of the same activity among its customers. Mark Throndson, director of product marketing, said customers often leverage standard IP such as a piece of USB IP, as it is “probably much better to leverage somebody’s standard implementation and the various compatibility testing and certifications that it’s already gone through from the supplier than going and rolling their own, over and over again.”

MIPS believes that in addition to the inherent value in terms of core functionality, the ecosystem is just as important. “It’s standards, it’s the breadth of software and an ecosystem around a standard microprocessor architecture in the industry—and the value on that is huge,” he said. “It makes a lot more sense in most cases for companies to leverage a standard architecture like MIPS to gain access to tools, software and surrounding components on the SoC than to ‘roll your own’ in that regard.”

Low-power considerations for reusing IP
When it comes to low-power considerations of IP re-use, there are two areas not governed by standards: power consumption and area.

“You can still meet the standard but consume lots of power or consume lots of die area, so what we’re doing is making sure that for that particular standard the area and power numbers are still attractive to the point where customers consider integrating that piece of IP on their chip,” said Navraj Nandra, director of analog/mixed signal marketing at Synopsys. “Maybe three years ago in the data center/cloud computing-type market, it was all about speed. Customers would come to us and say, ‘We want the fastest thing possible.’ Now they are saying, ‘Well, actually we want the same speed but we want the lowest power solution that we can have.’ We’ve had to change some of our design approaches while still meeting the standards. The re-use model still applies, but we’ve had to figure out new techniques for reducing the power consumption for these interfaces.”

Synopsys has been using techniques such as voltage mode output drivers for high-speed SerDes because they are lower in power consumption, although they are more sensitive to noise.

Process considerations
Ideally, IP providers try to make sure that the hardware they generate will synthesize into a wide variety of process technologies and a wide variety of cell libraries, so the customer has a lot of choices to make in terms of process, cost, power and area.

Tensilica’s Martin said the company considers how something will work on the next-generation process using the next-generation library. “There is always a demand for additional characterization data so people can understand the tradeoff choice. We believe that most of the tuning of the foundry specifics to the higher-level RTL that we generate is actually done by the cell libraries and specialized IP generators, for example for memory, analog/mixed-signal and interface blocks. Those are the areas where foundry and process-specifics really play. We want to remain with good digital RTL that maps across a whole range and gives good results in many different technologies.”

However, some IP is more sensitive to the process technology that it needs to be implemented in than others, noted MIPS’ Throndson. “The more you get to actually having to do a full physical implementation of the IP to make it real in a particular process, the more that case is true. In the case of a USB, it’s the actual USB PHY that is more process-specific. To actually use this and verify that it operates correctly in that particular process node and do testing of it, people end up doing test chips. It becomes very process-specific, so you have to be very aware and have a plan effectively for which nodes you are offering your IP in.”

On the other side, he said, MIPS’ core IP is fully synthesizable as soft cores and can be used in a variety of process nodes and flavors from a number of different foundries.

Synopsys also supports many different foundries—all of the big ones and some of the smaller ones such as SMIC. Nandra pointed out that what customers are asking for now from a re-use perspective is footprint compatibility between the IPs. If they purchase something from one foundry, and they decide that for second source or whatever reason they want to go to another foundry, they want that hard macro from Synopsys. They want the pin placement and the size of the macro to be, if not exactly the same size—as close as possible so it can be a drop-in replacement between Foundry A and Foundry B.

Is that realistic? “In one design, we went with that target. We had to change the internal layout of the designs so much because the two foundry design rules were different even though they were both 40nm, but actually the design rules are very different. The goal from the customer’s perspective was met because the pin placement and the size of the outline were exactly the same. But in order for us to do that we had to do some very, very clever layout [tricks.] That is the true IP re-use test,” Nandra said.

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