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Week In Review: Design, Low Power


Power always has been a function of cost. The more power required, the more it costs to run a device, both in dollars and carbon footprint. This makes the breakthrough in fusion ignition at Lawrence Livermore National Laboratory all the more noteworthy, and one that could have significant implications for the future of computing, from data centers to rechargeable batteries in automobiles, robot... » read more

Week In Review: Design, Low Power


Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

Week In Review: Design, Low Power


Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

Week In Review: Design, Low Power


Infineon Technologies acquired Syntronixs Asia, which specializes in precision electroplating, a key process in the assembly process of semiconductors. Syntronixs Asia has a workforce of more than 500 people and has been a major service provider for Infineon since 2009. “Through this acquisition, we have made another important step to strengthen the resilience of our supply chain,” said Tho... » read more

Week In Review: Manufacturing, Test


Government policy The National Security Commission on Artificial Intelligence (NSCAI) this week submitted its final report to Congress and the President. The goal is to develop a national strategy to maintain America’s AI advantages related to national security. As part of the long and complex report, the NSCAI came to a sobering conclusion: “The U.S. government is not prepared to defend t... » read more

Week In Review: Design, Low Power


Tools Synopsys introduced Euclide, a next-generation hardware description language (HDL)-aware integrated development environment (IDE). Euclide aims to enable earlier detection of bugs and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and UVM development. It assists correct-by-construction code development th... » read more

ISA Ownership Matters: A Tale of Three ISAs


An instruction set architecture (ISA) is crucial to the development of processors and their software ecosystems. In the last half century, the majority of ISAs have been owned by single companies, whether product companies for their own chips/systems or processor IP companies who licensed their processors to chip developers. Does ISA ownership matter? Let’s consider three proprietary ISAs a... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Third Point, a hedge fund, released a letter, saying that Intel needs to explore its strategic alternatives. This includes the breakup of the chip giant. Obtained by Yahoo and others, the letter says Intel needs to decide “whether Intel should remain an integrated device manufacturer” and should divest certain failed acquisitions. Here’s another analysis of the sit... » read more

RISC-V Verification Challenges Spread


The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

Speeding Up AI With Vector Instructions


A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort. Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, elim... » read more

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