Week In Review: Design, Low Power

Nuclear fusion’s potential impact on IC design; RISC-V verification, embedded development, new cores; testing network cybersecurity; funding for GPNPU IP.


Power always has been a function of cost. The more power required, the more it costs to run a device, both in dollars and carbon footprint. This makes the breakthrough in fusion ignition at Lawrence Livermore National Laboratory all the more noteworthy, and one that could have significant implications for the future of computing, from data centers to rechargeable batteries in automobiles, robotics, and mobile devices. Controlled fusion has been in the works for decades, and theorized for more than a century. There are still questions about when and how this will ultimately be used, whether it can be scaled sufficiently, and how it will affect energy prices, sustainability — and semiconductor design if there is, indeed, a cheap and plentiful energy source. Nevertheless, the importance of an inexpensive and nearly inexhaustible clean source of energy cannot be overestimated.

Fig. 1: Harnessing the power of 192 lasers to create nuclear fusion. Source: Lawrence Livermore National Laboratory

Electromigration and other aging factors are becoming more difficult to manage as chipmakers start developing out heterogeneous 3D-IC architectures. Reliability degrades as temperature rises.


Imperas Software updated its ImperasDV solution for RISC-V processor verification. Verification IP options have been extended to include riscvISACOV, a set of SystemVerilog source functional coverage libraries for all of the ratified instruction extensions and the first release of the privilege mode libraries to be used in conjunction with the effects of asynchronous events during verification. It also adds architectural validation test suites for RV32E, RV64E, Zc, and Zmmul specifications. Additionally, NSITEXE certified the Imperas RISC-V reference models for its NSITEXE Akaria processors, which include RVV1.0 compliant vector processor and multi-threaded scalar processor for a range of automotive and industrial applications.

Codasip launched SecuRISC5, an initiative to provide highly verified and secure reference designs combining Codasip IP and third-party technology. “Security is the ‘feature’ that people often fail to see the value in, but everyone knows they need. Another important aspect is that without security, there is no safety, and we are therefore adopting a holistic approach. We will help our customers integrate RISC-V safety and security by providing more than secure cores,” said Jamie Broome, vice president of Automotive and Products at Codasip.

Siemens Digital Industries Software announced that its Sokol Flex OS software now supports RISC-V embedded development for creating customized, Linux-based systems. It includes built-in security to monitor and detect common vulnerabilities and exposures and is commercially supported with updates and security patches, including a toolchain for software performance analysis.

Andes Technology announced a new 3-stage 32-bit RISC-V CPU core to target embedded processing and IoT applications. It also uncorked a RISC-V multicore 1024-bit vector processor for applications with large volumes of data.

Breker Verification Systems introduced a library of automated test generation IP elements targeting RISC-V processor cores and SoC platforms.

MIPS debuted high performance RISC-V multiprocessor IP with out-of-order processing and coherent multi-threaded, multi-core, multi-cluster scalability.

Ventana Micro Systems announced high performance RISC-V processor chiplets and IP with an eight wide, aggressive out-of-order pipeline, enterprise class RAS, virtualization, security features, top-down performance tuning, and system IP such as IOMMU and advanced interrupt controller.

XMOS said that its software-defined SoC platform for IoT device development is now compatible with RISC-V.

Data centers, embedded, automotive

Keysight Technologies introduced a high density 8-port 400GE Quad Small Form Factor Pluggable Double Density (QSFP-DD) modular network cybersecurity test platform for data center network equipment manufacturers and operators. The test platform can drive hyperscale application and cybersecurity test performance, including encrypted traffic loads, and can generate up to 3+ Tbps of Layer 4-7 traffic, 5+ billion concurrent connections, 2.4 Tbps of transport layer security (TLS) traffic, and 2.4 million TLS connections per second. Additionally, Synergy Design Technologies will use Keysight’s user equipment emulation solutions to create a network test environment supporting the development and troubleshooting of its software-based 5G Smart RAN solution.

Systems developed specifically for their environments increasingly are using adaptive control to stay within power budgets, but this is turning out to be a lot harder to implement than most people expected.

Infineon Technologies launched a new Source-Down MOSFET 3.3 x 3.3 mm² PQFN product family in the 25-150 V classes with Bottom-Side (BSC) and Dual-Side Cooling (DSC) variants. In the Source-Down concept, the MOSFET die source contact is flipped toward the footprint side of the package, which is then soldered to the PCB, and has an improved clip design on top of the chip for the drain contact and market-leading chip-to-package area ratio. The family targets DC-DC power conversion in server, telecom, battery protection, power tools, and charger applications.

Quadric, maker of general purpose neural processing unit (GPNPU) IP that runs both machine learning inference workloads and classic DSP and control algorithms, added $10.0M to its Series B round with new investment from Xerox Ventures and Mesh Ventures. This brings the round to $31.0M. “We are rapidly ramping up our commercial teams to engage customers and continuing to expand our top-notch engineering organization to deliver our GPNPU and our world-class software tools for application development,” said Veerbhan Kheterpal, co-founder and CEO of Quadric.

Hamamatsu Photonics adopted Siemens Digital Industries Software’s mPower software for the power integrity analysis of its next generation of optical semiconductor devices for scientific measurement, medical, and automotive markets. “Power integrity analysis is a critical technology for us, because our optical IC products need to achieve extremely high performance and reliability in order to meet stringent functionality requirements,” said Masaaki Matsubara, manager for the second design group, Design Center, Solid State Division for Hamamatsu Photonics.

Renesas Electronics and Fixstars Corporation jointly developed a suite of tools that allows optimization and fast simulation of software for autonomous driving systems and advanced driver assistance systems (ADAS) specifically designed for the R-Car SoC devices from Renesas. The tools aim to make it possible to rapidly develop network models with highly accurate object recognition from the initial stage of software development and reduce post-development rework.

MathWorks added a hardware support package for Infineon’s latest AURIX TC4x family of automotive microcontrollers to its Simulink products. It can be used to validate use cases, rapidly and automatically generate the embedded software, and test algorithms before silicon is available.

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