The Shocking Side Of 3D

Balancing performance and protection will be a much bigger deal when chips are stacked together.

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By Ann Steffora Mutschler
The pesky static charge that builds up on your clothing when you forget the dryer sheet is more than just a nuisance when it comes to manufacturing ICs. Add 3D structures and process scaling to the mix and the challenge of adequately protecting those devices grows significantly.

While this problem used to be largely an afterthought, the charged-device model type of electrostatic discharge—which occurs frequently in the manufacturing process—has taken on new meaning in 3D stacking.

“Not only do you need to do the die, the package, testing—now with stacked die it is an extra step, and one that will create more problems for the CDM,” said
Dian Yang, general manager and senior VP of product management at Apache Design Solutions. “The problem will be worse.”

Much worse, in fact. Matthew Hogan, technical marketing engineer for LVS in Mentor Graphics’s Design-To-Silicon Division, said that when moving to smaller geometries the ESD events themselves become more destructive because the area that they take out is still the same but with more dense circuitry. “Also, because ESD as it is defined is protection against a specific current and voltage specification, those ESD structures stay roughly the same size, regardless of the process node that you are implementing them in. That means you are taking up more real estate for the active logic in your circuitry but you still need the ESD structures to have approximately the same dimensions and look-and-feel as you instantiate them.”

It really is about finding the compromise. “To do the perfect ESD structures takes up the entire chip area and you can protect the inverter that is in the middle of the chip perfectly. Somewhere along the line there is a compromise: Either it’s a lowering of the ESD standards that you are protecting against or some other engineering decisions that get made so that you can adequately protect your circuit while giving as much room and flexibility to the people that are designing it,” Hogan explained.

Another issue is how to formulate the ESD discharge paths. “In 3D, it gets very complicated,” said Yang. “It goes from one die to another die or it goes through the TSV (through silicon via)–that’s a very complicated issue.”

After that, simulation and analysis must be considered. “Even if we know how it behaves or the damage it could cause, now how do we simulate it during the design process? Before we only needed to consider the simulation for the 2D cases. Now we have to look at 3D structures and simulate. That’s much worse than the 2D case,” he said.

This will happen even in 2.5D structures, where an interposer is used to connect together parts from multiple vendors. “The silicon interposer may be from one vendor, or it may be coupled with some other SoC guys, but all different vendors need to contribute to solve this problem. This interaction, this modeling, the data passing, all these things are getting worse.”

Reliability issues
From a low-power perspective, Hogan observed there might be some reliability concerns if thin oxide gates are connected to high-voltage rails. Thin oxide is very attractive because the thinner the oxide, the lower the voltage that can be used to switch with a threshold. And because power is a function of current and voltage, you can get lower power out of the device, which in electronics that means lower heat, smaller packages, fewer heat sinks.

However, very thin oxides break down a lot easier than a thick-oxide gate and careful attention must be paid to how the device is connected to the rest of the system. “Previously you might not have cared whether or not you had properly tied off your wells to the right power supply, particularly if you’ve got different power domains that switch themselves on and off,” Hogan noted. “But when you are using thin oxide or low-power transistors, now you probably do care. In 3D IC environments when you are using silicon interposers or when you are stacking dies, one thing you want to make sure of is when you’ve done a verification of the chip as a standalone die. Maybe it’s got a connection through the microbump pad up to the next chip sitting on top of it. You need to go through and make sure all of the transistors are in the right domains and all of the power signals are hooked up correctly.”

It could be that low power transistors try to drive high power transistors that are in different power domains, for example. In the context of 3D assembly, this could create reliability issues simply because there are different power domains that the signal crosses, or because the signal is communicating with different ESD type structures such as a level shifter or back-to-back anti-parallel diodes. Signals that do cross power domains need these sorts of protection circuits so that they can survive ESD-type events.

Now what?
Hogan said it is critical to understand the topologies in the design to identify the critical structures and whether there is sufficient protection around them. Design teams must also understand where the signals are going to come from. “If you are trying to protect against the HBM (human body model), there is one set of criteria. If you’re trying to protect against CDM then you have another set of criteria. In the 3D IC realm, because there is stacked silicon, you’ve got silicon interposers and it really gives more degrees of freedom for how to protect all of these things that are connecting together.”

Previously, he explained, if there was a real pin-out going to the PCB up through another chip, there was a lot of area that needed protection. Butt now if it is essentially an internal signal, there may be more room for negotiation with the different parties because the big pad ring might not be needed and the larger size transistors are not needed to push all of that current and voltage through the external pin, across the PCB, up to the other chip, he said.

Ideally, the good intentions happen early on, but then something unexpected happens and compromises have to be made.

Apache’s Yang said the water is still murky in terms of how best to deal with ESD in 3D ICs. “I don’t think that we have a clear picture yet. People just say it is becoming worse, but how to deal with it is still a big question…I think that we are way early, honestly.” The reason is that 3D structures still, at this moment, are only used in standard components such as DRAM or flash, and memory makers are still at the early stage, he said.

And for the needed ESD simulation and analysis on those 3D memories, how it is done today is anyone’s guess. “Honestly, I don’t know. This is very secretive. Anything related to 3D, as soon as you touch on some real practical solutions all the IC vendors just shut off – they don’t talk. Either they don’t know how to do it, and I don’t know if that’s true or not, or they want to protect it because they think it is an advantage.

When asked about its work on 3D IC, TSMC confirmed it has been working closely with customers on 3D IC technology, and together they have delivered some promising results. The company declined an interview request but said via email, “Until now, TSMC did not see any significant ESD impact, but we will continue monitoring and evaluating this subject along the way.”

In terms of applying 3D technology to applications beyond memory, Yang said drivers could include mobile devices and Wide I/O. He believes Wide I/O will push a lot in terms of the 3D structure, whether it is silicon interposer-based or stack-based with a TSV. “The questions remain: Is Wide I/O practically ready? Is the cost-effectiveness there? Will low-power DDR3 relieve some pressure on the Wide I/O adoption?” On the other hand, Yang personally thinks Wide I/O will be a very big driver for 3D structures.