April 2011 - Page 2 of 5 - Semiconductor Engineering

Understanding Formal Verification Concepts
By Various Writers - 28 Apr, 2011 - Comments: 0

In today’s complex system on chip (SoC) designs, verification has become a real challenge. Register transfer level (RTL) and gate-level simulations are effectively used for verifying the functional correctness of any design. However, as designs are growing in size as well as functionality, more and more test vectors need to be created and run to get reasonable test coverage. In addition to th... » read more

Turning Chaos Into Order
By Jack Harding - 27 Apr, 2011 - Comments: 0

By Jack Harding It would be unthinkable to begin this article without recognition of the disaster the Japanese people are enduring, even as this is written. My friends and colleagues are as safe as they can be, so far; thousands are lost. But it takes no imagination to appreciate the psychological and very real overhang of nuclear toxins changing a society for a decade. The sad irony of the... » read more

What’s Missing In Verification
By Ed Sperling - 27 Apr, 2011 - Comments: 0

System-Level Design talks with Mentor Graphics, Cadence, and an Accellera member about what's changing in verification--and where the missing pieces are.   [youtube vid=alb3dncca4o] » read more

Wafer Demand: Good to Grow in 2011
By Joanne Itow - 25 Apr, 2011 - Comments: 0

By Joanne Itow The foundries are ramping 32nm/28nm production but that’s only one of the reasons wafer demand is forecast to grow at above average rates this year.  MEMS and sensors will help to grow wafer demand at the ≥1000nm technology nodes.  Wafers processed at ≥1000nm technology will grow by 10.2% in 2011.  That’s on top of the 25% growth experienced in 2010. Microcontrolle... » read more

Experts At The Table: Yield Issues
By Ed Sperling - 22 Apr, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Effects Unknown
By Ed Sperling - 22 Apr, 2011 - Comments: 0

f you really want to know what’s going on inside the IC design world, pick up a copy of the annual reports of the largest foundries. Then triangulate that with the earnings reports of the largest makers of computers and mobile electronics and the makers of EDA tools and IP. All three areas are experiencing a massive uptick, which is good news considering the travails of the past couple of ... » read more

Redefining Mobile
By Ed Sperling - 22 Apr, 2011 - Comments: 0

Mobile devices traditionally have been defined by their power source. In the future, they will likely be defined by where data is processed, which has enormous implications for designs. The good news for many of these devices is that the work on battery-power devices will pave the way for greater efficiency in those with a plug, allowing much more intelligent decisions about tradeoffs betwee... » read more

Changing The Flow Of Technology
By Ed Sperling - 19 Apr, 2011 - Comments: 0

A mad scramble is underway—quietly, of course, because it involves competitive positioning—to prepare for stacked die. No one wants to be left out of this transition, regardless of whether they’ve branded it as pure fiction in the past. And no one wants to be caught unprepared, even though they’re not sure exactly when this shift will take place. But what’s particularly interesting... » read more

Photonic Cloaking Devices
By Michael Watts - 16 Apr, 2011 - Comments: 0

by Mike Watts The Romulans are tricky so and so’s, running around cloaked — at least they have to de-cloak to fire (The Romulans are a Star Trek species that use a cloaking device). It turns out the British Army has got a similar idea, and has demonstrated that it can hide a tank using cameras and screens. At Photonics West in January, I saw a presentation that showed the cloaking of ... » read more

ESL Power Optimization Flow Requires Ecosystem
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate. The ITRS’s most recent projection provides some insight as to current market d... » read more

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