Understanding Formal Verification Concepts

Increasing design size and functionality results in too many test vectors and takes far too much simulation time. Assertions can help.


In today’s complex system on chip (SoC) designs, verification has become a real challenge. Register transfer level (RTL) and gate-level simulations are effectively used for verifying the functional correctness of any design. However, as designs are growing in size as well as functionality, more and more test vectors need to be created and run to get reasonable test coverage. In addition to the time and effort needed to create these test vectors, the simulation time increases substantially. Moreover, for some cases, it is not very easy to create test vectors, which renders the traditional method of simulation not very effective. This is where formal verification pitches in to help.

This paper describes formal verification concepts and the differences between formal and simulation techniques, especially in the context of assertion-based verification. The assertion-based verification flow and some of the formal verification algorithms are also discussed in detail. Last but not the least, a few applications of formal technology in the context of ASIC designs are also listed. To download this white paper, click here.

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