June 2011 - Page 3 of 5 - Semiconductor Engineering

5 Ways To Cut Power
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine. While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern ... » read more

System Models Are Changing
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Pallab Chatterjee Historically system-level modeling was based on making sure there were no timing crashes on the main data bus. After that it was multi-core conflict resolution, distributed memory routing and, most recently, verifying the correct core actually has access to the correct memory with the data that is relevant being available. All of these areas are now subject to an additi... » read more

Too Soon For Wide I/O
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler When 3D ICs are prevalent, Wide I/O is sure to be there. But where does the technology stand today? Considering the amount of buzz and hype, it would be easy believe it is being implemented in production designs today. Wide I/O is a very brute-force way of solving the problem of trying to get latency down with a high-speed memory interface, explained Navraj Nandra,... » read more

Managing Physical Effects
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Managing the physical effects from manufacturing is becoming increasingly critical as designs grow in size and process geometries dive lower. Just keeping track of these effects in a billion-gate design is a daunting task. At advanced manufacturing nodes, the capacitance and inductance effects make the design much harder—and that includes both on-die and off-die ... » read more

Low Power Simulation
By Luke Lang - 16 Jun, 2011 - Comments: 0

By Luke Lang Once in a while I’m asked if it’s necessary to check power and ground connections with VDD/VSS-aware simulation on a physical (PG) netlist. The short answer is: “No, as long as you have run LP structural verification. But if it will help you sleep better at night, then go for it.” For the longer answer, keep reading. In order to run VDD/VSS-aware simulation, one must ha... » read more

The Tough Metric: Energy-Efficiency
By Barry Pangrle - 16 Jun, 2011 - Comments: 0

By Barry Pangrle Jem Davies, fellow and vice president of technology at ARM, gave a keynote address on Computing Power and Energy-Efficiency Tuesday morning at the AMD Fusion Developer Summit in Bellevue, Washington. His scheduled appearance at the summit led to much speculation and rumor a while back, especially within the context of the ARM versus x86 battle for market share in the tablet ar... » read more

Low-Power Solutions At DAC
By Bhanu Kapoor - 16 Jun, 2011 - Comments: 0

By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

Need To Know Basis
By Ed Sperling - 16 Jun, 2011 - Comments: 0

There’s a great and often over-used line out of movie scripts when the hero stumbles upon something that doesn’t make sense and he’s told, “That’s on a need-to-know basis.” The same seems to be true in low-power engineering. While everyone talks about the need for reducing the power inside of chips, the reality is that only the really advanced SoC and processor companies are taki... » read more

Experts At The Table: Are We Cool?
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation. LPE: At 28nm we have clock ... » read more

Physical Effects Affecting Design
By Ann Mutschler - 16 Jun, 2011 - Comments: 0

With the increase in analog content in today’s designs, the industry is facing a real challenge in terms of how to perform mixed-signal verification at the functional level, at the SPICE level and down to physical implementation of the DRC rules. Joseph Davis, product manager for Calibre interactive and integration products at Mentor Graphics, explained there are three things driving what�... » read more

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