By Michael P.C. Watts Printed electronics does not involve printing electrons, but you get the idea. Every start up and corporate research group have their own version of printed electronics using different semiconductors, dielectrics or metallization strategy. As usual, I like to focus on patterning. There are 4 patterning strategies, conventional resists and imaging, imprint, flexograph... » read more

The momentum behind vertical stacking of die, either in 2.5D or 3D configurations, is growing. So is the argument about just how big a change this will actually represent. To a large extent, it all depends on where you’re sitting. Xilinx CTO Ivo Bolsens calls 3D stacking a disruptive technology. From an FPGA standpoint, which potentially could be used as a programmable addition to any SoC,... » read more

In the move to stacked die, one of the biggest issues is power. While chips using leading-edge processes already address this issue effectively through a variety of advanced techniques, the big question mark is what happens with the older technologies. The answer may not be quite so simple. While it’s still possible to use technology developed at older process nodes, it may not be exactly ... » read more

By Ann Steffora Mutschler In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O. There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, wha... » read more

By Pallab Chatterjee Solid-state flash memory still isn’t cheap, but performance, reliability and power have transformed it from a niche market into a mainstream one. And it’s about to get even more popular. At the recent flash memory summit, the majority of the sessions focused on the further penetration of NAND flash into the consumer electronics product segment. NAND technology alrea... » read more

By Ann Steffora Mutschler Driven by the need to reduce power but increase bandwidth in smart phones and other mobile devices, system architects are grappling with new technologies to take system performance to the next level. Wide I/O, as well as some DDR technologies, are vying for center stage in tomorrow’s leading-edge mobile designs. “The big technological advancement that allows a ... » read more

By Ed Sperling The rule of thumb at 90nm—still one of the mainstream process nodes—has been that test is something you do when a chip is done. You attach electrodes on either side, make sure the signal comes through clearly, and that the SoC functions properly. Try the same thing at 40nm, with multiple power islands, multiple voltage rails, lots of third-party IP and usually a slew of p... » read more

By Kurt Shuler Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip (SoC) market over the last couple of years. As reported by EE Times, Gartner’s latest “Hype Cycle for Semiconductors... » read more

Selling more tools to fewer large customers has always seemed like a tough proposition for the tools industry. Remarkably, it seems to be getting easier. In fact, the more chipmakers push into advanced geometries, the more engineering managers are speaking up at industry conferences about a direct correlation between the number of tools they buy and the amount of time and money they save. Th... » read more

By Jack Browne Normally summer is a time where most people slow down, relax, take vacations and the pace slows down accordingly with the seasonal ebb and flow of our industry. But not this summer. Exhibit A, B, C, D and so on: This past month has demonstrated the profound element of change. Mostly in our wallets. The stock market volatility and global economic disruptions have echoed (an... » read more