The 3D Power Factor

There won’t be any shortcuts in re-using IP developed at older process nodes…at least in the short term.


In the move to stacked die, one of the biggest issues is power. While chips using leading-edge processes already address this issue effectively through a variety of advanced techniques, the big question mark is what happens with the older technologies.

The answer may not be quite so simple. While it’s still possible to use technology developed at older process nodes, it may not be exactly the same technology as was originally developed at those older nodes. In some cases, it will be completely different. Much of the IP that will be “re-used” will likely be IP that was developed specifically for stacked die, not for older chips.

The key advantage is that the process technology has been tested, worked out, and modified appropriately for 3D, not that the IP design won’t need to be tweaked. In the analog world, this may still amount to a significant redesign of that IP.

The big culprit here is power, and power budgets on stacked die won’t be any more lenient than on two-dimensional structures. In fact, they may be more constraining because the die will be thinner. In 2.5D stacks it will be easier to use thicker die, but the power constraints will likely be similar. Battery technology isn’t changing quickly enough, and more features with better graphics and faster performance are likely to absorb most of the gains of approaches such as Wide I/O.

The result is that stacking of die won’t get easier. And while there will be time savings and yield improvements once this packaging approach ramps to commercial viability, it will take time to get the whole ecosystem updated and aligned. When it comes to SoCs, there still are no shortcuts, and probably won’t be for years to come.

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