October 2011 - Page 4 of 4 - Semiconductor Engineering

The End of the DRAM Era – Flash Spending Surpasses DRAM
By SEMI - 06 Oct, 2011 - Comments: 0

By Clark Tseng, SEMI Industry Research and Statistics, Taiwan The semiconductor memory industry has a long history of fluctuating market cycles. The DRAM sector in particular has gone through a few bad cycles and witnessed quite a few consolidations in the past ten years or so.  However, DRAM continues to be one of the most important and capital intensive sectors in the semiconductor indust... » read more

Power Intent Formats: Power Domain
By Luke Lang - 06 Oct, 2011 - Comments: 0

By Luke Lang Starting this month, I will be writing a series of blogs inspired by “Dueling Power Formats”. The article correctly points out that there are currently three power formats: CPF, UPF 1.0, and IEEE 1801. Some designers will find themselves in a position of having to choose a format. Others will need to work with both formats. Regardless of which position one is in, these LP desi... » read more

Intel’s Claremont Near-Threshold Voltage IA Core
By Barry Pangrle - 06 Oct, 2011 - Comments: 0

By Barry Pangrle Intel announced many new technologies at its recent Intel Developer Forum (IDF) held from Sept. 13-15 in San Francisco, but the one announcement that jumped out at me was the unveiling of its work on a near-threshold voltage (NTV) processor named “Claremont.” For this exercise, Intel chose an older Pentium design to help minimize the number of variables the engineers would... » read more

Experts At The Table: Mobile Design Challenges
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation. ... » read more

Performance Plus Lower Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

A new race is beginning in the SoC world. While performance has been supplanted by battery life as the top goal for the next process node, that prioritization isn’t going to last. The ultimate challenge will be to achieve both—higher performance with substantially lower power. This is the subject of research inside of dozens of companies and universities, and there are several different... » read more

Are We There Yet?
By Ann Mutschler - 06 Oct, 2011 - Comments: 0

We’ve been talking in the industry for as long as I can remember about hardware and software co-design and I’m always curious to hear how that it progressing….or not. I posed this question to Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation synthesis group who is constantly in touch with engineering teams. His take is that hardware and software teams are... » read more

Ultra-thin wafers for 450mm FD-SOI on schedule
By Various Writers - 03 Oct, 2011 - Comments: 0

While much of the focus on the impending move to 450mm has focused on the equipment challenges, the wafers themselves are of course the primordial consideration. Predictions are starting to mount up linking the move to 450mm with a move to fully-depleted silicon-on-insulator (FD-SOI). So the question needs to be asked: will the wafers be ready? Engineered substrates like SOI wafers need to ... » read more

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