October 2011 - Page 3 of 4 - Semiconductor Engineering

45nm and Below Grabs 24% of Wafer Demand in 2011
By Joanne Itow - 11 Oct, 2011 - Comments: 0

By Joanne Itow The economic malaise in Europe and the U.S., along with the natural disasters around the world, have put a damper on 2011 semiconductor sales. Heading into the holiday buying season, consumer confidence is low and inventories are higher than preferred. OEMs are, at best, cautious and in most cases, pessimistic about their markets. Semico expected a shakeout in the tablet mark... » read more

The Genealogy of DFM
By David Abercrombie - 07 Oct, 2011 - Comments: 0

By David Abercrombie Family histories are all the rage these days. With the advent of online databases, what was once a difficult and expensive task is now accessible to anyone with Internet access. Not only can you investigate census data, immigration records, and military service records with ease, but some sites also allow you to access information compiled by other site members. All of a... » read more

Noise Coupling Analysis
By Arvind Vel - 06 Oct, 2011 - Comments: 0

By Arvind Shanmugaval Integrating digital and mixed-signal IP blocks in SoCs poses a considerable challenge to verification of power/ground and substrate noise. Traditional methods of power supply noise analysis are unable to meet the demands of today’s highly integrated designs with multiple low- power design techniques. Existing methods also do not provide sufficient capacity or the capabi... » read more

Limits For TSVs In 3D Stacks?
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics. Stacking die holds the promise of becoming... » read more

Redefining Systems Around Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Engineers have been talking about system-level power budgets since Moore’s Law reached 65nm, but as power becomes a critical element of any design with or without a plug the definition of what constitutes a system is changing. While most SoC engineers think of the system as an IC, power increasingly is playing a significant role in the subsystem, and even in the larger syst... » read more

Low Power Drives Performance And TCO
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Pallab Chatterjee A common theme at this year’s Custom Integrated Circuit Conference was the reduction of power and power management while increasing data throughput. Historically, the show has featured new techniques for ultra high accuracy and brute force improvements in performance at all costs. The main theme this year was that in a world of mobile endpoint devices, the goal is to get... » read more

Thermal Modeling Held Back By Outdated Standards
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area. Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs the... » read more

Energy Vs. Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler The terms power and energy are used almost interchangeably these days, but understanding and clearly articulating how to optimize embedded designs for maximum energy and power efficiency can make a big difference in a design. At a physics level, energy = power x time, whereas power is the rate of energy in a given time window. When the focus is specifically power, ... » read more

Power and Noise Integrity for Analog/Mixed-Signal Designs
By Various Writers - 06 Oct, 2011 - Comments: 0

This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements. To download this paper, click here. » read more

The Hidden Costs Of Test
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling As complexity grows in SoCs, so does the ability to accurately test them. That helps explain why there are so many different types of tests and so much confusion about what to use to perform those tests, when to test, and where in the flows to include those tests. But what’s less well known is that tests done improperly also can give false results, labeling good chips as bad�... » read more

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