August 2012 - Page 4 of 6 - Semiconductor Engineering

G450C To Align Vendors During 450mm Transition
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By David Lammers Innovation and synchronization among multiple companies do not often go hand in hand. But for the 450mm wafer transition to provide its full benefits, chip makers and their suppliers will need to do more than a simple wafer size scale up. That may lead the Global 450 Consortium (G450C) to serve as the proving ground for efforts to more closely match the electrical results o... » read more

3D-IC Impact On Computational Lithography?
By Ann Mutschler - 16 Aug, 2012 - Comments: 0

While 3D devices and technology such as through-silicon vias (TSVs) definitely complicate matters in the design, verification and manufacturing space, one might assume there would also be an impact on the computational lithography tools that are used to ensure printability. Have no fear. Industry experts assure us that this is not the case. Lithography expert Chris Mack acknowledged that ... » read more

LED Firms Mull New Wafer Sizes And Materials
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus Seeking to reduce the cost of solid-state lighting and related applications, LED manufacturers are taking a page from the IC industry: They are looking at larger wafer sizes and new materials in the fab. Today, the state-of-the-art LED fab is a 150mm (6-inch) facility, but a large percentage of these plants are still using 50mm (2-inch) substrates. The vast majority of LED s... » read more

What’s After NAND Flash?
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus For years, many have predicted the end of flash memory scaling, particularly NAND, but the technology continues to defy the odds as it moves down the process curve. Still, there are signs that the floating gate structure in today’s flash memory is on its last legs. The floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio. And ... » read more

Challenges For Patterning Process Models Applied To Large Scale
By Various Writers - 16 Aug, 2012 - Comments: 0

Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist... » read more

2012 IP Challenges For The Semiconductor Industry
By Various Writers - 16 Aug, 2012 - Comments: 0

A company’s intellectual property (IP) is fundamental to its ability to innovate, develop new technologies and methods, and move forward in a competitive industry. SEMI is acutely aware that what distinguishes its key industries from many others is the relatively high percent of revenue that is reinvested into R&D. On average, semiconductor equipment and materials companies invest 10-... » read more

Preparing For Change
By Ed Sperling - 16 Aug, 2012 - Comments: 0

Throw out the most optimistic and the most pessimistic predictions about the future of the foundry model and you probably arrive at a reasonable approximation of how things will actually play out. It's clear that the number of customers at the front end of process technology will shrink after 20nm. It simply costs too much to design and manufacture a chip, and there aren’t enough markets c... » read more

Inflection Points
By Ed Sperling - 15 Aug, 2012 - Comments: 0

Semiconductor Manufacturing and Design talks with Paul Boudre, chief operating officer at Soitec, about FinFETs, industry inflection points, the end of life for planar transistors, bulk CMOS vs. SOI, the differences between fully depleted and partially depleted SOI, and the FD-SOI ecosystem. [youtube vid=8ZhfJLkImlk] » read more

Experts at the Table: Stacking the Deck
By Ed Sperling - 10 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of Eda2Asic Consulting. ... » read more

Analog Hits The Power Wall
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Analog design teams are starting to encounter the same physical issues that digital design engineers began wrestling with several nodes ago—only the problems are more complicated and even more difficult to solve. At advanced nodes digital circuitry is susceptible to an array of physical effects ranging from heat, electromigration, electromagnetic interference and electrosta... » read more

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