G450C To Align Vendors During 450mm Transition

The Global 450 Consortium will seek to achieve die-to-die matching and other performance goals as it pushes toward the 450mm transition. With relatively few companies expected to build 450mm fabs, the G450C members are in a strong position to ask for coordinated technical targets.


By David Lammers
Innovation and synchronization among multiple companies do not often go hand in hand. But for the 450mm wafer transition to provide its full benefits, chip makers and their suppliers will need to do more than a simple wafer size scale up.

That may lead the Global 450 Consortium (G450C) to serve as the proving ground for efforts to more closely match the electrical results of production tools.

Ron Rinfet, director of Intel’s 450 program, said it will take “a lot of work to align the technical roadmaps, which is one of the roles of the G450C. The suppliers will use this as an opportunity to introduce incredible changes.”

Die-to-die matching is one of the two technical challenges facing the consortium, the other being the scale-up of the wafer size and the expected cost savings. In a presentation during Semicon West, Rinfet showed a slide detailing the role film variability in die to die matching, which will require cooperation on die-level electrical test results, uniform plasma density, improved thermal and thickness control, optimized pumping, and improved film stress management.

The 450 transition program, started within Sematech but now under CNSE’s management, has included tool performance specifications for several years, with Sematech program managers conducting day-long seminars on the performance targets of a range of 450mm tools.

Earlier this year, Qualcomm’s senior vice president of engineering, Michael Campbell, spoke at the Advanced Semiconductor Manufacturing Conference in Saratoga Springs, N.Y. He emphasized Qualcomm’s desire to make electrically compatible versions of the same mobile phone processors at two or more fabs.

Today, Qualcomm must use four different libraries for its foundry partners, adding to design complexity. And Campbell said getting two fabs within the same foundry to produce electrically compatible chips is a struggle. He pointed to the synchronization efforts at G450C as a means of solving the tool and fab matching goals needed by high-volume fabless companies such as Qualcomm.

Early on, the consortium’s main job is to move tools into the new NFX (NanoFab Xtension) building, nearing completion at the College of Nanoscale Science and Engineering (CNSE) in Albany, N.Y. From 2013 onward, the pilot line will serve as a test bed for methods to more closely align tool outputs, among other goals.

The G450C members currently include Intel, IBM, GlobalFoundries, Samsung, and TSMC, along with CNSE. Kirk Hasserjian, a vice president at Applied Materials, said there may be only five or six companies processing 450mm wafers, reflecting a savagely Darwinian selection process. During the current 300mm generation, about 25 companies are processing 300mm wafers, down from about 75 at the peak of the 200mm diameter.

In a consolidating industry, companies may rely more heavily on common components in order not to waste R&D dollars, Hasserjian said, emphasizing the need for the chipmakers to move to 450mm at roughly the same time using similar design rules. The clout of such few equipment buyers puts the G450C members in a strong position to ask for coordinated technical targets as they innovate their patterning, deposition, and other processes. And the equipment companies must deliver a further three nodes on 300mm tools as well, requiring leading edge equipment at both the 300mm and 450mm wafers sizes—an expensive prospect.

Scaling itself will become increasingly thorny as 450mm production begins late in this decade. “DRAM, flash, and logic devices are all hitting fundamental barriers, requiring more atomic-scale deposition,” said Akihisa Sekiguchi, a corporate marketing director at Tokyo Electron Ltd. (TEL). Sekiguchi quoted dire forecasts from consultancy IBS predicting that the cost per function is now on an upward curve. “Concurrent development on 300 and 450 tools at the bleeding edge is not sustainable,” he argued.

With R&D funds already stretched thin by the demands from device scaling, equipment companies have a favorable view of Intel’s roughly $4 billion investment in ASML, which is aimed primarily at readying EUV scanners capable of processing 450mm wafers at high throughputs. (Dean Freeman, manufacturing analyst at Gartner, said he was told that Intel made a private investment in Nikon to prepare the 450mm-capable immersion ArF scanners).

While several executives at major equipment vendors said they would welcome similar investments from Intel to bolster their 450mm development programs, a senior IBM executive said the Intel-ASML relationship may prove to be unique. ASML holds a virtual monopoly in the EUV tool field, providing them with more leverage than any other vendor over when the complete 450mm toolset will become available. Without ASML getting fully on board, 450mm at 10nm and below design rules wouldn’t go forward. For all the other major tool types, more than one vendor exists, relieving Intel of the need to make direct investments, the IBM executive speculated.

The G450C leadership points to the consortium’s investment in a 450mm wafer bank as a means of supporting all the interested tool vendors, according to Michael Liehr, general manager of the G450C. “We are making a large investment in wafers,” said Liehr, who earlier worked at IBM before joining CNSE.

The consortium wants to have full process capability in place by 2014, ideally with two suppliers for each major tool type, said David Skilbred, director of program coordination at G450C. The consortium management is busy talking to interested suppliers now. By the second phase, G450C will be working with both on-site and off-site suppliers, he added.

Imec also is making plans for the 450mm transition, though its focus differs from that of the G450C group. “Our focus is on process development,” said Ludo Deferm, vice president of business development at Imec. The Flemish government is contributing about $125 million toward construction of a clean room, set to be finished by 2015, that will be used for 10nm and beyond process development on 450mm wafers.

The European equipment industry is a significant employer in Europe, and the companies look to Imec as a place where their 450mm tools can be used for leading-edge process development. But Imec is not directly involved in developing the 450mm toolset, and looks to cooperate with G450C in that effort. “All of our core programs will move to 450mm wafers in the next seven years,” he said, including lithography, transistor and interconnects, 3D, and the Insite program which includes the largest fabless IC vendors.

Source: G450C

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