The Next Materials Race


Trade wars are costly on many fronts, and a trade war between the United States and China is bound to cause a variety of problems that no one anticipated. But in some areas, there may be a silver lining. And where there is no silver lining available, other materials may suffice. For decades, big chipmakers have been squeezing the entire semiconductor supply chain in a race to double the num... » read more

The Big Blur


Chip companies, research houses, foundries—and more recently large systems companies—have been developing alternative technologies to continue scaling power and performance. It's still not obvious which of those will win, let alone survive, or what they will do to the economics of developing chips. For more than five decades, the biggest concern was scaling devices in order to save money... » read more

Cheaper Fan-Outs Ahead


Packaging houses continue to ramp up fan-out wafer-level packages in the market, but customers want lower cost fan-out products for a broader range of applications, such as consumer, RF and smartphones. So in R&D, the industry for some time has been developing next-generation fan-out using a panel-level format, a technology that could potentially lower the cost of fan-out. But there are ... » read more

450mm And Other Emergency Measures


Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

Changing Economics In Chip Manufacturing


The foundry and equipment businesses are poised for significant changes that could affect the balance of power far beyond just the semiconductor manufacturing sector. It’s no secret that the number of companies developing new chips at 7nm is shrinking. There will be even fewer at 5nm. The business case for moving forward is that density must provide a competitive edge. But that density imp... » read more

The Road To 5nm


There is strong likelihood that enough companies will move to 7nm to warrant the investment. How many will move forward to 5nm is far less certain. Part of the reason for this uncertainty is big-company consolidation. There are simply fewer customers left who can afford to build chips at the most advanced nodes. Intel bought Altera. Avago bought Broadcom. NXP bought Freescale. GlobalFoundrie... » read more

Behind The Intel-Altera Deal


Intel completed its $16.7 billion acquisition of Altera this week, wrapping up what is arguably the semiconductor industry's most important M&A transaction of 2015. Time and numbers will tell exactly how important. There are two big challenges to making this deal work. One involves a big shift in direction away from simply shrinking features to include new architectures and packaging approac... » read more

Increasing Challenges At Advanced Nodes


Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Analysis: Applied-TEL Scrap Merger


After several delays due to a myriad of complex regulatory issues, Applied Materials’ proposed deal to buy Tokyo Electron Ltd. (TEL) has been scrapped. It appears that the U.S. Department of Justice (DoJ) stepped in and blocked the deal. Now that the deal has been terminated, Applied Materials and TEL are separately re-grouping, and are back to where they originally started as fierce compe... » read more

Unraveling The Mysteries At IEDM


In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

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