Cheaper Fan-Outs Ahead

Demand for lower cost drives R&D for panel-level packaging. But which size?


Packaging houses continue to ramp up fan-out wafer-level packages in the market, but customers want lower cost fan-out products for a broader range of applications, such as consumer, RF and smartphones.

So in R&D, the industry for some time has been developing next-generation fan-out using a panel-level format, a technology that could potentially lower the cost of fan-out. But there are a multitude of economic and technical challenges in bringing panel-level fan-out into mass production—there are no standards and several companies are developing fan-out with different panel sizes.

In addition, today’s fan-out and panel-level fan-out are somewhat different and it’s difficult to transfer one process to the other. In production for several years, current fan-out technologies involve packaging a die in a round wafer format in 200mm or 300mm wafer sizes. In fan-out, individual dies are embedded in an epoxy material in a round wafer. The dies are then processed and diced, resulting in a chip housed in a fan-out package.

In panel-level fan-out, though, the package is processed on a large square panel or an LCD substrate. A 500mm x 500mm panel, for example, can process 4.54 times as many die as a 300mm wafer, according to a paper from STATS ChipPAC and Rudolph Technologies. By increasing the number of die per substrate, a vendor could see huge productivity gains and lower costs over today’s fan-out processes, according to the companies.

Fig. 1: Comparison of number of die exposed on 300mm wafer to number of die on panel. Source: STATS ChipPAC, Rudolph

Looking to help bring the technology into the market, A*STAR, ASM Pacific, Fraunhofer and ITRI separately have formed panel-level fan-out R&D consortiums or are planning to launch one. In addition, several packaging houses—such as Amkor, ASE/Deca, Nepes, Powertech, Samsung, STATS ChipPAC and others—are either exploring the technology or putting it into production. Both Intel and TSMC are also exploring panel-level packaging.

The problem? There is no standard panel size in the market and each entity appears to be developing panel-level fan-out with a different panel size. “I understand over eight companies are now working on (panel-level) fan-out,” said Seung Wook Yoon, director of product technology marketing at STATS ChipPAC. “For the panel size, some are developing 500mm x 500mm. Some people are using 500mm x 600mm. Some people are using 450mm x 450mm and others. The panel sizes are all different. This is a challenge.”

Fig. 2: Organizations and panel sizes. Source: Company data/Semiconductor Engineering

Fig. 3: Company panel sizes and delivery dates. Source: Company data/Semiconductor Engineering

Despite the apparent lack of standards in the market, some are moving ahead in panel-level fan-out with production slated by late 2017 or in 2018. But the mass adoption of the technology won’t emerge until much later. “The volumes to drive panel for any single part probably won’t be there until 2019,” said Jan Vardaman, president of TechSearch International.

Other packaging houses, however, are still taking a wait-and-see approach, and for good reason. Besides the standards issues, it costs $100 million to $200 million to build a panel-level production line. A company must have enough volume to ensure a return, although it’s still unclear if there is enough demand to justify the investment right now.

It also presents challenges for equipment makers. Some have developed panel-level packaging tools, but many equipment vendors are reluctant to invest in panel tools in a big way until a standard emerges and the market takes off. “That’s the reason that a lot of large companies have been reluctant to develop equipment specifically for panel, because there is no consistency on what the panel size would be,” Vardaman said. “If an equipment company is going to make an investment, they would want to be certain that there is more than one company that would be buying their equipment.”

Clearly, though, the market cannot support eight panel-level fan-out vendors. There is only room for a handful of players, according to other analysts, who added that it will take a year or two before the market is sorted out. As a result, wafer-level fan-out will remain the mainstream technology for the foreseeable future.

The case for panels
The fan-out packaging market is hot. This sector is expected to grow from $244 million in 2014 to $2.5 billion by 2021, according to Yole Développement.

Apple, Qualcomm, NXP and others are developing chips using today’s fan-out. Fan-out enables customers to integrate multiple dies in a single package with more I/Os than traditional packages. It doesn’t require an interposer, making it less expensive than 2.5D/3D.

Fig. 4: Comparison of fan-in, flip-chip and fan-out. Source: Yole Développement

Today, there are three main types of fan-out technologies—chip-first/face-down; chip-first/face-up; and chip-last, sometimes known as RDL first.

Fig. 5: Chip first vs. chip last. Source: TechSearch International.

Qualcomm and others, however, have been vocal about wanting a lower cost fan-out packages using a panel-level format. “The argument for panel is to lower the cost,” Vardaman said. “Honestly, I don’t think the user cares what the format is as long as they get a lower cost. There is an interest in something that gives you lower cost as long as it meets the reliability requirements and the yield is sufficiently high.”

As stated above, panel-level fan-out enables a vendor to process more dies on the substrate at higher productivity. For example, a vendor can process 1.64 times as many die on a 300mm x 300mm square panel, as compared to a 300mm round wafer, according to STATS ChipPAC and Rudolph. A 600mm x 600mm panel produces 6.5 times as many die at productivity rates at 96% or more, according to the companies.

In another example, a 300mm wafer can accommodate 5,945 dies at a die size of 4.05mm x 2.6mm. In comparison, a 600mm x 600mm panel can handle 28,350 dies, according to the companies.

Fig. 6: Productivity increase that can be expected when processing on 600mm x 600mm panel over 300mm diameter wafer. Source: STATS ChipPAC, Rudolph

Panels make sense from that standpoint, but it’s challenging to put the technology into production. “There are two important items to focus on. One is the bill of materials set-up and the other is the manufacturing line and tools,” STATS ChipPAC’s Yoon said. “An optimized bill of materials is the most important factor for warpage control, die shift, and thus, yield and reliability. To control warpage, a solid bill of materials study for optimization in a process is required.”

Panel-level fan-out, in fact, has many of the same challenges as today’s fan-out using a round wafer format. In fan-out, a round wafer is formed by using an epoxy mold compound, which creates a reconstituted wafer. The dies are then placed on the wafer. The placement accuracy of the dies is critical. But at times, the dies move during the process, causing an unwanted effect called die shift. The wafer is also prone to warpage during the flow.

Panel-level processing is conducted at a much larger scale, so warpage becomes even more problematic. And generally, today’s processes are immature, making it difficult to develop panel-level fan-out at line/space features below 5-5µm. In contrast, today’s fan-out is migrating to 2-2µm and beyond.

“Wafer-based fan-out is likely to continue for advanced fan-out packages because of superior patterning and deposition process capabilities,” said Stephen Hiebert, senior director of marketing at KLA-Tencor. “Larger fan-out packages with multiple devices and higher levels of integration will be hard to migrate to panel fan-out, due to challenging process requirements, such as achieving minimal dimensions and across-substrate uniformity.”

Compounding the challenges is that there are two basic approaches for panel-level fan-out. The first approach makes use of a high-density-interconnect (HDI) PCB substrate. The other uses thin-film substrates based LCDs.

The PCB approach combines the advantages of embedded die technology from fan-out with the low-cost PCB infrastructure. “It’s a good idea to utilize the PCB infrastructure,” STATS ChipPAC’s Yoon said. “However, yield is low due to the nature of the substrate process technology. Finally, it has seen very limited production even after 10-plus years of development.”

There are other issues. “A failed substrate containing embedded die, whether embedded first, middle or last, will have a higher cost than a failed HDI board,” said Arthur Keigler, chief technology officer at TEL NEXX.

In comparison, LCD substrates are cheap, but the industry must develop several new tool types for this approach. “(The LCD approach provides) very few of the processes necessary to make a package,” said John Hunt, senior director of engineering at Advanced Semiconductor Engineering (ASE). “It gives you the handling capabilities of a large panel, but that’s about all it gives you.”

Clearly, panel-level packaging has some gaps. “It’s not simply the processing equipment,” Hunt said. “You have to put the whole infrastructure together with a panel process.”

Who’s doing what?
To help develop the infrastructure, there are two types of entities working on panel-level fan-out–commercial companies and R&D consortiums. Some companies belong to one or more R&D groups. Others are going it alone.

On the R&D front, for example, Germany’s Fraunhofer last year launched the so-called Panel-Level Packaging Consortium. Intel, Amkor/Nanium, Suss, Unimicron and others are part of the group.

This group is developing the key building blocks for panel-level packaging. Fraunhofer has also assembled a panel-level processing line using a 610mm x 456mm format. The target is to develop 30mm x 30mm package sizes at 5-5μm.

Fig. 7: Fraunhofer’s panel-level line. Source Fraunhofer

Meanwhile, Hong Kong’s ASM Pacific last year also launched a separate R&D effort, dubbed the Fan-Out Wafer/Panel-Level Packaging (FOW/PLP) Consortium. Dow, Huawei, Indium, JCET/JCAP and Unimicron are part of this group, which is developing a chip-first technology based on two panel sizes—340mm x 340mm and 508mm x 508mm.

Also last year, Taiwan’s ITRI started a panel-level fan-out project based on Gen 2.5 technology, which is 400mm x 500mm. “Our project, which is at its early stage and scheduled to be completed in three years, focuses on providing a solution in transforming the outdated panel lines for panel fan-out packaging applications,” said Huey-Huey Lo from ITRI’s Display Technology Center. “(There is an) emphasis on RDL process through investigating the required equipment and establishing relevant technologies based on our existing Gen 2.5 line which had been used for flexible AMOLED development, e.g. coating, thin/thick film process, photolithography patterning and debonding.”

And not to be outdone, Singapore’s Institute of Microelectronics (IME), part of A*STAR, is planning to launch a panel-level fan-out consortium based on Gen 3 technology, which is 550mm x 650mm, according to Vempati Srinivasa Rao, senior industry development manager at IME.

Fig. 8: Consortium members. Source: Company reports/Semiconductor Engineering

If that isn’t enough, several packaging houses are developing the technology. For example, ASE recently invested in fan-out specialist Deca. Under the plan, ASE is in the process of installing Deca’s panel-level technology within ASE’s production site in Kaohsiung, Taiwan. ASE is looking at both 300mm x 300mm and 600mm x 600mm.

“Deca has the capabilities in-house to mold the panels and do the die placement,” ASE’s Hunt said. “We are working with other vendors on all of the other equipment sets to make the panels. So we don’t see any roadblocks.”

ASE plans to have a pilot line by 2018, with production slated by 2019. Deca then will bring up the same technology within its own site. “You can fit a lot of die on a panel,” Hunt said. “So we don’t see that we would need that capacity before then.”

Indeed, for some time, ASE has been shipping traditional fan-out, which can meet the current demand in the market, he added.

Meanwhile, Nepes plans to move into panel-level fan-out production later this year, which is based on a 650mm x 700mm format. “The market application is for mobile,” according to a marketing manager at Nepes.

Then, later this year, Samsung Electro-Mechanics is expected to outline its plans for panel-level fan-out using an LCD-based technology, according to multiple sources.

Still others are taking a wait-and-see approach. Amkor, for example, is working with Fraunhofer and other consortiums. “We have our own internal investigation as well,” said Ron Huemoeller, vice president of R&D at Amkor. “We have not fixed a panel size at this moment as we continue to judge the market and the real need for panel-based fan-out. Investment hurdles are large for this manufacturing format with a very uncertain return.”

Indeed, it costs more than $100 million to build a production line. And with a panel-level line, the production output will increase significantly, so packaging houses need customers with huge volume requirements.

This is where the business model becomes shaky. “It’s a huge investment. If there are enough customers or sound business engagements, it makes sense. But it’s a risky project,” STATS ChipPAC’s Yoon said. STATS ChipPAC has been working on its own panel-level fan-out, but it hasn’t made a final decision on the panel size yet.

TSMC, meanwhile, is exploring the idea of developing fan-out on 450mm wafers, but it has no plans to switch to that wafer size right now. And not to be outdone, Intel has a panel-level development line in Arizona. Intel is developing a general panel-level technology based on a 500mm x 500mm format.

Wanted: equipment
Today, fan-out is produced on 200mm and 300mm equipment. The lack of a panel-size standard, coupled with the uncertainty in the market, presents some challenges for equipment vendors in the panel arena.

Generally, LCDs, PCBs and solar cells are produced on panels. Some but not all of the equipment used in these industries can be adopted for panel-level packaging. Other equipment could be developed, but it would be expensive.

Then, some wafer-level packaging equipment vendors have developed tools for panel-level fan-out. Many other wafer-level equipment makers are looking at panel technology, but they aren’t jumping into the market for several reasons.

Most don’t have the resources to support all panel sizes. Tool vendors could build a system that supports a panel size or two. Yet it’s not feasible to sell only a few tools to a limited customer base, so many are waiting on the sidelines until a standard size emerges and the market takes off.

“Clearly, it’s a huge investment for equipment development,” said Markus Wimplinger, director of business unit technology development and IP at EV Group. “This can be done if the critical mass is there, but we have to wait and see if it happens at a larger scale. And then there is no question that we will go for it.”

There are other issues. “You have to look at the economics,” said Kevin Crofton, president of SPTS Technologies and vice president at Orbotech. “Would a capital equipment company be able to make money on a panel-level packaging format system? If you run the numbers, you might only have to sell 80 pieces of equipment. Maybe it’s a 100, but it’s a very low number of equipment to satisfy the entire world’s requirement if everything went panel. How can you make money at that? Who will make money at it?”

So how does an equipment vendor support panel? “From an architecture standpoint, it’s probably a piece of equipment that addresses the wafer format applications,” Crofton said. “And then, it’s another piece of equipment that is panel directed. If an equipment vendor is doing what’s right for their customers, you would try and make it as universal as possible, so you could do multiple applications in the same platform. That would be the approach that a company like SPTS and Orbotech would take, as opposed to one flavor for a particular application.”

Regardless, packaging houses could assemble a panel-level fan-out production line using existing tools. In lithography, for example, traditional steppers can be adapted for panel-level fan-out.

Then, in another option, Screen Semiconductor Solutions recently introduced a direct imaging system for panel-level fan-out. Using a 355nm laser and four imaging heads, Screen’s tool directly images a pattern on a die. It enables a throughput of 70 panels-per-hour for minimum resolutions at 5-5μm.

The industry also is working on panel-level electrochemical deposition (ECD), which handles the plating processes. “TEL NEXX anticipates that ECD for panel will adopt many of the features used in wafer tools as tighter deposition requirements are implemented on panel,” TEL NEXX’s Keigler said. “For example, to control simultaneous filling of blind vias and line feature uniformity, it will be advantageous to use advanced organic additive packages that require ion-exchange membrane separation between anode and cathode.”

Some panel-based system-in-package (SiP) applications require double-sided deposition. This has not been used in wafer tools but is common in PCB systems.

This capability must be available in advanced panel ECD tools. “Fan-out and SiP build-up structures vary widely in dielectric, molding, seed layer and metal layer thicknesses,” Keigler said. “All of these factors result in a variety of edge configurations to which ECD contact and fluid seal must be made. This is true for both wafer and panel applications. And finally, panels are significantly flimsier than wafers. New capabilities are required in the ECD module to provide a uniform reaction on a surface that may be moved by the fluid.”

In metrology, meanwhile, a tool must address film variations and warpages at feature heights at 50 to 100µm. “In most fabs, the sensitive nature of the chips on wafers/panels precludes the use of contact-based techniques such as stylus profilometry,” said Vamsi Velidandla, senior marketing manager at KLA-Tencor. “One approach is to use a multi-mode optical design combining optical profilometry and broadband reflectometry into the same measurement head. The optical profiler has to be designed to overcome the surface roughness, reflectivity and slope limitations of existing interferometry-based systems.”

Profilometry is the technique that measures the profile of a surface. Reflectometry characterizes objects. “The multi-mode approach enables the simultaneous measurement of photoresist film thickness and copper plating thickness before the resist is stripped from the wafer/panel,” Velidandla said.

There are some tool gaps, however. “Ultimately, there will be a space for panel-level packaging,” SPTS’ Crofton said. “It’s going to be constrained by the need for uniformity across the panel and uniformity within die across the panel. That technical challenge hasn’t been solved.”

On the other hand, there are a lot of major players working on the problems. But given the lack of standards and technical hurdles in the arena, it’s unclear if the momentum will accelerate or dissipate over time.

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rroy says:

You forgot Georgia Tech PRC with their glass panel approach that Corning is pushing.

Mark LaPedus says:

Hi rroy. Thanks for bringing that up. Here’s more information on that:

Venky Sundaram says:

Thanks Mark. Nice article.

Dev Gupta says:

Mark, a very good attempt. The point that needs to be made however is that regardless of whether FO WLPs are built on a reconstituted 300 mm wafer or a 600 mm sq panel, they ALL suffer from one huge problem, the WASTAGE of space on the wafer / panel that is used to accommodate the Fan Out to cater to the coarse pitched BGA needed to connect to the next level of packaging ( typically a Motherboard made of coarse pitch PCB, though these days we see more and more finer pitch HDI ). So long as the BGA pitch is not shrunk ( say because the MB can’t handle finer pitch ) this wasted area ( mostly mold compound ) on the reconstituted FO WLP wafer will remain large and make FO WLPs more expensive than FC BGAs on substrates ( made at coarser pitch hence cheaper than the periphery of FO WLPs ). For SINGLE CHIPS the ideal case to replace FC BGAs with FO WLPs would be when the die is large but do not have too many I/Os going down as BGAs to the MB. Everyone seems to be accepting Apple using TSMCs inFO WLP as a validation for the use of FO WLPs for Processors ! Can we really say that it made sense cost wise when a single supplier is now providing both die and package and at a single bundled price ? Bundling the A10 gave a lot of competitive edge to the Foundry but can the A10 be enough justification for other large Fabless customers to abandon the ability to bargain that comes with using FC and multiple suppliers ? You yourself have stated that QCOMM has been pushing for Panel level FO WLPs so as to cut costs. It so happens that QCOMM actually stayed with FC for the Processor they brought out last year at the same time as the A 10 ! For MULTI CHIP MODULES that require dense interconnects between the dies, FO WLP can be a cost effective replacement for fine pitch Interposers but some of the inherent technical issues of FO WLP ( at least for its face down – die first version ) like die shift / warpage could be show stoppers and some of the more updated FC substrate technologies like SWIFT would be better. There is a fog of apple to orange comparisons claiming better electrical performance of FO WLPs compared to FC, this is true only for FC built on Core substrates ( through vias in thick cores add inductance ) but not so if a Coreless substrate is used. The FC on Coreless has the advantage of being a die last process on a low inductance substrate and is superior to FO WLP in terms of cost. For more on all this look up the Webinar I gave yesterday at SST on ” Dense Off Chip Integration “.

Mark LaPedus says:

Hi Dev, Excellent insights. How long can we extend FC BGA?

Dev Gupta says:

Hi Mark : actually thin coreless substrates for FC BGAs w/ 5 um L/S is already out there under customer evaluation. One has to recognize that there is nothing unique / exclusive about FO WLPs including the much ballyhooed info WLP. So long as one uses the same type of smaller format ( 300 mm ) and better / more expensive tools ( e,g. Litho ), FC substrates of similar L/S is no sweat. Of course compared to most FO WLP flows a FC would require wafer bumping, then assembly ( placement, TC – FC bond, UF ) but then there will also be some savings w r to FO WLPs because tools ( like Platers ) will no longer be under used like when you process a reconstituted FO WLP wafer with just a fraction of its area occupied by dice ( only 50 % for the inFO WLP w/ the A10 in it ). The more established FC has several other temporary advantages ( yield, specially for MCMs ) over FO WLP which is still under development. To cut through all the hoopla on TSVs & FO WLPs, just check out my Webinar

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