Increasing Challenges At Advanced Nodes

GlobalFoundries’ CTO discusses new materials, stacked die, EUV, and 10nm planar FD-SOI.


Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation.

SE: Where do you see problems at future nodes?

Patton: At the device level, we have to be able to pattern these things. We need films with the right comformality and selectivity. And we still need to strain materials. Materials innovation is at the core of a lot of this technology—straining and high-k materials, all kinds of materials to be able to etch and pattern. With self-aligned double or quadruple patterning you have to have the right films. We’re still looking at novel materials for the film—how do you grow silicon germanium or germanium or other III-V materials? That involves epitaxy. You have to be able to dope these things. If you take silicon germanium and get up to 80% or more, you start to lose boron doping. The resistivity goes up. There are alternatives like gallium.

SE: How is that working out?

Patton: We’ve done an implant process, but we really need an epi process. We’ve worked on precursors. And do you use SOI finFETsor bulk finFETs? With bulk finFETs, the problem is the junctions. There is not a lot of overlap capacitance. You have to be able to deposit source/drain dope films into very small channels. We also need to continue to engineer high-k/metal gate, and then there’s problems with contacts. How do you engineer copper? What’s beyond copper? There are materials that don’t have as good a bulk resistivity as copper, but when you start looking at how copper is starting to increase as you shrink it, due to scattering, these things are less sensitive. But that involves a lot of work involving deposition and the processing steps around it—CMP and others—to support these alternative materials.

SE: In the past, you knew what was coming several nodes in advance. Can we keep on track with new nodes and all of these changes?

Patton: That’s a fair question. When we have time, we’ve dropped some of these things into a more mature node to really vet them. But we’re running out of time.

SE: There is more talk about node skipping these days. What’s going on?

Patton: You have to be careful about node names these days. One person’s 7nm is another person’s 8nm or 9nm. We have a 10nm and 7nm program in Malta as a result of work that was being done in Fishkill. We’re riding both and we’ll see where the market goes.

SE: What do you see as the most important metrics going forward? Is it still PPA?

Patton: From a customer perspective, yes. But you still have to balance that with manufacturability. If we are unable to ramp the process and the product when the customer needs it, then that’s a problem.

SE: Are you seeing a push toward performance per watt or compute power per watt?

Patton: Different customers have different metrics. PPA is a broad one.

SE: With the combination of IBM and GlobalFoundries, what’s changed?

Patton: The challenge is ensuring we deliver a value proposition for future technology nodes. How we define 10/7nm is very critical. People have started extrapolating from 20nm that there is no value proposition going forward. I disagree. But it’s not just about scaling. It’s looking at other ways we can deliver value—features and capabilities. FD-SOI is a great example of that. It’s great that you get finFET performance at 28nm cost. But what’s really interesting for me is that you get software control. You can turn chips, blocks and circuits on and off. It’s a whole new degree of freedom for the designer. The RF technology that came over with IBM—SiGe, RF-SOI—those are very unique, differentiated capabilities. The ASICs business was another attractive business. There are a lot of people who want to make use of the infrastructure. To be able to use a proven design methodology with all the library pieces to get products out sooner is very sooner.

SE: How about stacked die?

Patton: That’s another piece. We had a big 2.5D and 3D program at IBM. We have an offering that’s very heavily used by the ASIC team to win business.

SE: Will we see new combinations?

Patton: We could. The one we advertise in 2.5D is where we took analog/mixed signal chips and married that with ASIC chips. Here was a case where you needed the performance of the SiGe chip—you couldn’t do it with the ASIC chip—but there was no reason to put the logic or IP in a SiGe bi-CMOS process. It was a much more optimized solution taking a 45nm ASIC logic chip and marrying that to a 2.5D package with two RF chips for the transceiver and receiver. But we’re also shipping 2.5D and 3D parts today. The one that’s public is the Micron engagement. In both 2.5D and 3D there are logic chips in those parts. They tend to start out with more niche applications. As the volumes increase, it helps drive the cost down. And then people see it’s shipping and start to realize this is real and they can use it. We’re definitely seeing an uptick in requests for quotes for 2.5D solutions.

SE: There’s been a lot of talk about interconnect problems. Where do we go next?

Patton: We’re working on alternative metallurgies. While they may not have as good a bulk resistivity as copper, when you start talking about refined dimensions they may offer some significant advantages.

SE: Is it harder to work with?

Patton: There’s still a lot of work ahead to get it ready for manufacturing. There is a lot of activity on self-forming barrier as a way to improve resistance. You can put a film on top of the copper line, then it diffuses through to create a metal oxide layer on the interface, and it’s a much thinner layer so you have more the material that you need with a low resistance.

SE: What becomes the next transistor structure? Is it lateral nanowire and then vertical nanowire?

Patton: We’re looking at nanowires and vertical transistors. Both of those have some serious challenges. But they’re candidates at the 5nm node, whenever that happens.

SE: Will it happen?

Patton: Yes.

SE: Will 450mm ever happen?

Patton: That’s not clear.

SE: One issue with advanced nodes is the cost of equipping a fab. How long does equipment last at advanced nodes?

Patton: We put a huge focus on tool re-utilization. As we defined 10nm, that was a major focus for us—re-using the tools we put in place for 14nm. We have 80% re-usability.

SE: IBM made a lot of noise about air gap technology. When will that show up?

Patton: In the server arena they are very risk-averse. They have to get systems out on a schedule. They’re making extremely big chips, too, so the issue of chip-package interaction puts a lot more stress on the back end of line when you have a chip of that size. Looking at the benefit at that time and the chip-package interaction, our decision was not to go with it. That was back at 32nm. But air gap is an important part of our [joint development] alliance. It will definitely be used in our foundry technology.

SE: At what node?

Patton: We haven’t announced that yet, so I can’t say.

SE: It seems as if the market is splintering in many directions. How do you figure out where to place your bets?

Patton: Those are not huge changes. We have a pretty broad portfolio of derivatives on 40nm and 28nm. Compared to doing 7nm, it’s a pretty small investment. FD-SOI plays right into that. A number of these products don’t need to be at 7nm. A key focus is ultra low power. I believe 22nm FD-SOI fits the sweet spot. You don’t drive yourself to deep double patterning for the back end of line.

SE: Will FD-SOI be extended to 14nm?

Patton: We wouldn’t do 14nm FD-SOI. We would want a bigger jump than that. It would something closer to 10nm.

SE: Does that require a finFET?

Patton: No, it would be planar. If you go to finFET, you would lose the back body biasing. That’s a key attribute.

SE: So the only change would be multi-patterning, right?

Patton: Yes, and we would have to make sure we tuned it to the right point so you get the best cost optimization. That’s what we did at 22nm, where you keep away from double patterning. If you’re going across one of these cliffs, like double patterning, you want to go a ways beyond it so you get a return on the investment.

SE: You’re just rolling out 22nm. What’s the timing on 10nm? Is that a two-year cadence?

Patton: We’re not sure yet because 22nm will be a long-lived node.

SE: There’s a lot of confusion about different process flavors and what different foundries call each process node. What’s the impact on GlobalFoundries?

Patton: Most people have figured that out. At 7nm, where you start hitting points where you drive additional mask levels, you’ll see a lot more alignment between different players. As you push it further, there are a lot more masks for not a lot of return.

SE: Along those lines, where is EUV at this point?

Patton: It’s making progress. We just finished a review. It’s performing much better in terms of power. But for research we’re not as concerned about power as availability. We want to make sure it keeps running, because we’re looking at cycles of learning. It’s doing well. They’re going to get there on power. My bigger concern is availability. It’s a complex technology. Can they keep it running enough to get the cost down? There’s still work to do on resists and on masks. If we can get the pellicle to work, it will alleviate some of the pressure on defects. I don’t see 7nm launching with EUV. It could be brought in selectively.

SE: How about DSA?

Patton: Defects are the biggest challenge. There is progress. But it’s something we’re pushing hard in Albany.


witeken says:

Is the last question answered? Intel’s still the only one, yet they made little noise about it..

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