tag: strain

Electrochemical Absorption of Hydrogen in Structured Palladium Thin-Film Electrodes (Univ. of Bristol)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "Exploring Electrochemical Methods for Precision Stress Control in Nanoscale Devices " was published by researchers at the University of Bristol. Abstract "Tuning the local film stress (and associated strain) provides a universal route toward exerting dynamic control on propagating fields in nanoscale geometries and engineering controlled interactions between th... » read more

A Comparative Study With Horizontal and Verticals FETs (POSTECH, Georgia Tech)
By Technical Paper Link - 26 Aug, 2025 - Comments: 0

A new technical paper titled "Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET" was published by researchers at POSTECH and Georgia Institute of Technology. Abstract "For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of hori... » read more

GAA Transistors: 3D Atomic-Scale Metrology of Strain Relaxation and Roughness via Electron Ptychography (Cornell, ASM, TSMC)
By Technical Paper Link - 14 Jul, 2025 - Comments: 0

A new technical paper titled "3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography" was published by researchers at Cornell University, ASM and TSMC. Abstract "To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes dow... » read more

Die-To-Die Stress Becomes A Major Issue
By Ann Mutschler - 14 Jan, 2021 - Comments: 2

Stress is becoming more critical to identify and plan for at advanced nodes and in advanced packages, where a simple mismatch can impact performance, power, and the reliability of a device throughout its projected lifetime. In the past, the chip, package, and board in a system generally were designed separately and connected through interfaces from the die to the package, and from the packag... » read more

The Good And Bad Of 2D Materials
By Katherine Derbyshire - 27 Feb, 2019 - Comments: 0

Despite years of warnings about reaching the limits of silicon, particularly at leading-edge process nodes where electron mobility is limited, there still is no obvious replacement. Silicon’s decades-long dominance of the integrated circuit industry is only partly due to the material’s electronic properties. Germanium, gallium arsenide, and many other semiconductors offer superior mobili... » read more

Increasing Challenges At Advanced Nodes
By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

What’s After 10nm?
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions. Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based ... » read more

Mobility Gets A Boost With Expanded Epi Applications
By Applied Materials Writers - 17 Jul, 2013 - Comments: 0

By Jeremy Zelenko Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of an Applied Materials announcement made today is to extend epitaxial deposition from PMOS to NMOS transistors. Implementing an NMOS epitaxy (epi) process in addition to the estab... » read more

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP
By Various Writers - 17 Jul, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die ... » read more

VLSI Kyoto – The SOI Papers
By Various Writers - 19 Jun, 2013 - Comments: 0

By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all b... » read more

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