Mobility Gets A Boost With Expanded Epi Applications

Expanding epitaxial deposition from PMOS to NMOS transistors will improve performance for next-generation mobile devices.


By Jeremy Zelenko
Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of an Applied Materials announcement made today is to extend epitaxial deposition from PMOS to NMOS transistors. Implementing an NMOS epitaxy (epi) process in addition to the established PMOS epi enables chipmakers to further boost their transistor performance and deliver next-generation mobile computing power.

With today’s announcement of a production-proven technology to enhance PMOS and NMOS transistors, Applied Materials is supporting industry efforts to meet the ever increasing demand for greater computational power for future mobile products. This increase in performance can support advanced capabilities such as improved multi-tasking, enhanced graphics and image processing, greater responsiveness, and more.

Epi is an essential building block for high-performance transistors, delivering a gain in speed equivalent to that obtained by scaling half a device node. It is a method of depositing, or growing, a monocrystalline film that takes on a lattice structure and orientation identical to that of the substrate.

The initial epi application was to deposit a blanket film to achieve a high-purity starting point for building semiconductor devices. At the 90nm node, the industry introduced selective epi in PMOS transistors by which films are deposited in specific areas of transistors to introduce stress by distorting the crystal lattice (Figure 1). In logic devices, this enables electricity to move more easily through the transistor, increasing its performance.

Figure 1. Larger atoms introduced during epitaxial deposition induce strain.

Selective epi for strain engineering has delivered drive current increases (faster speed) in PMOS transistors by up to 60 percent since 2003. To gain a similar boost and to increase overall chip performance, chipmakers are applying selective epi in NMOS transistors in their 20nm node devices. The NMOS transistor differs from the PMOS in that it requires tensile strain; PMOS transistors need compressive strain along the channel for performance enhancement (Figure 2). Applied’s announcement today unveils a highly manufacturable approach to enhance PMOS and NMOS device performance.

Figure 2. Compressively strained SiGe films in the source/drain region of a PMOS device significantly enhances mobility. Tensile strain in the NMOS transistor improves performance.

This video primer reviews the historical progression of epi. It also includes a look to the future where many in the industry expect epi to be used to replace silicon material in the channel regions with higher-mobility group IV & III-V materials. This would represent a major change that promises significant transistor performance enhancement in addition to the epi used in strain engineering.

—Jeremy Zelenko is the strategic marketing director for transistor and metallization products in Applied Materials’ Silicon Systems Group.

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