中文 English

CEO Outlook: It Gets Much Harder From Here

Experts at the Table, Part 1: As power/performance benefits shrink at each new node, engineers are turning to different chip architectures and new materials.

popularity

Semiconductor Engineering sat down to discuss what’s changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in front of a live audience at the ESD Alliance.


L-R: Wally Rhines, John Chong, John Kibarian, Jack Harding. Photo: Paul Cohen/ESD Alliance

SE: In the past, EDA has focused very heavily at the leading edge of design, but price, performance and power benefits are disappearing at 7nm and 5nm. So where does the industry go next?

Harding: We’re making 7nm chips and we’ve started 5nm IP development, and we share that concern. It comes down to how do we find customers with sufficient volume to justify the investment. The NRE for a 7nm chip is $25 million to $30 million, including mask set and labor. So it’s not for the faint of heart. The notion of, ‘We’re going to dabble with a piece of silicon and see if it sticks,’ is gone. These are existential decisions for many companies. The design starts are dropping off, and we continue to have concerns about the durability of that market. So we find ourselves looking at reuse approaches, such as chiplets and other approaches, which allow our customers to develop ASICs without the same financial overhead. That extends to all elements of the design, from the EDA tools to the IP to labor, compute and storage. The decisions we make today are all made around execution of the chip itself at the lowest reasonable cost model. That has caused us to do things we’ve never even consider.

Rhines: TSMC is reporting that 25% of their revenue is coming from 7nm, and 5nm risk wafers are starting this year or early next year. So the game of new technology nodes is not going away or frightening people off because of cost. It will still be a vibrant part of the business. But we’re also seeing a shortage of 200mm wafer equipment now because people are going back to older nodes. We’re seeing heterogeneous multi-chip packaging, fan-out wafer-level packaging, things where you can achieve performance goals without just shrinking feature sizes. That’s the way the industry has always worked. Moore’s Law has focused on feature sizes, but in reality we’ve been on a continuous learning curve and we’ll stay on that learning curve forever. And the cost per transistor will go down every year for the rest of our lives.

Kibarian: Dennard scaling stopped a long time ago. Clock rates stopped increasing. Since then we’ve had a few nice jumps. So high-k (dielectrics) was a good jump. FinFET gate was another good jump, and we’ll have another one with gate-all-around, and eventually a shift off of silicon for mobility. Those come very infrequently, but as an industry we need to give benefit to the world every year. So we need to now innovate many more ways. There is a renaissance going on right now because you can’t get these improvements the easy way anymore, which was scaling. We’re all going to have work harder to find opportunities. There are more niches to mine, as well.

Chong: As a sensor maker, we’re not at the leading edge. Our MEMS chips are 1 micron alignment width, and our ASICs are 180nm or 130nm. So we’re not living in that space. But as an outsider, we do see wafer sizes were an easy way to drive down costs, and that hit a wall at 300mm. People were talking about 450mm, and that never happened. And now we’re talking about line widths hitting a wall. So it probably will be opening up other avenues—not the easy ones—for more creative ways to gain performance at a lower cost.

Rhines: This is not a new phenomenon of diversification. It used to be that in the first five years of a node you did more than half of the lifetime revenue or wafers of that node. When we hit 130nm, that shifted suddenly so that the first five years was less than a third, and then the next five years and beyond was more than two-thirds, and it stayed that way since then.

Harding: In my first month on the job in 1984 at Zycad, which made hardware accelerators for boolean algebra, I went down to the Applied Physics Laboratory at Johns Hopkins for a semiconductor conference. Some folks from GE Intersil showed up and announced they were leaving the semiconductor industry because there would be no way to make a chip below 1 micron. I have huge confidence in our ability to figure this out. We are constantly finding ways and innovating new ways to deliver the goods. But I do believe an economic reality will play a role. We’re making reticle-size chips. The business people are telling the architects that staying on Moore’s Law is not an option and they have to innovate at the architectural level because the ROI is not there.

SE: There is certainly a boom at 200mm. But can you make a business out of that? There are lots of niches here, so collectively there is more demand, but the volumes and margins are lower.

Harding: We can’t make money in the older nodes because there are too many small, low-margin-centric companies around the world that are willing to sell older technology for 20 points of gross margin. About four years ago we decided to either ‘go big or go home.’ We did everything we could to move up the stack to become a tier-1 supplier with leading-edge finFETs. Otherwise we’d be forced to compete with smaller Asian companies that are basically giving designs away. In the ASIC business, if you’re making a standard product for yourself it’s perfectly fine, but we can’t make money there.

Rhines: For the EDA industry, this is a great business. Whether you’re doing 200mm or 300mm, you still need software. There’s been a new business putting resolution enhancement—optical proximity correction—in older node parts. There has been a plethora of new companies coming into the business that are designing with design rules that archaic by some standards, but they still need software. They still do verification and design. What has really helped the EDA industry is that a slew of people have joined the business of designing chips who never were there before. Some 180 companies have announced they will introduce autonomous vehicles, and 400 companies have announced they will introduce electric cars. Our fastest-growing group of customers are the Googles, Amazons, Facebooks. They’re doing chips, boards, everything. These people weren’t even on the roadmap 10 years ago. Now they’re big users. So the EDA end of this is great. I would caution we don’t need 180 autonomous vehicle companies and 400 electric car companies, so every party does come to an end and not all of them will survive. But in the meantime, they will buy a lot of EDA tools and software.

SE: There has been a big push toward heterogeneous design, so it’s not just a CPU or other type of processor. There may be lots of different processors, including CPUs, GPUs, DSPs, eFPGAs. What kind of challenges does that create in making sure these chips actually work?

Harding: The chips we make tend to have an ASIC die in the center, four stacks of HBM around the corners, interposers and 2.5D packages. That’s the baseline, and they’re really not chips. They’re modules. There are a lot of technical issues, including signal integrity, because there are all sorts of signals propagating around what are essentially miniature printed circuit boards. For me, the biggest issue is supply-chain alignment. So many people have to touch a part correctly in order to get it out the door in an acceptable time frame. What that means is we are no longer a chip company. We are a systems company. We have to understand all the elements of our customers’ systems—hardware, software, firmware, thermal effects, in order to get these chips out the door. Recently we’ve adjusted our resources, both people and technical, to accommodate that. But the biggest thing we did was spend massive amounts of time with our supply chain to get us all on the same page so we could pass the module development from company to company in order to have a working part.

Kibarian: To make these kinds of chips, you can’t put it all on a piece of silicon. It’s not possible. Even scaling won’t give you the density you need. So chiplets, and multiple chips in a package, has to happen. That pushes a lot of the technology risk—and a lot of the supply chain risk—onto chip companies, which have become systems companies. A fabless chip company used to be able to order from a foundry, send it to an OSAT to package it, and then they would sell it. Now it gets passed along to many different places. You buy from competitors and sell them completed chips. The analytics are growing massively because all of the chip and system companies are managing a much more complex supply chain. Traceability is a requirement. People want to know what set of tools that was assembled on and what is the exposure for other people who may have seen a similar problem. In the MEMS market, traceability is a major concern for them. The great benefit of system-in-package comes with a whole bunch of additional work for everyone in the supply chain. When you have an autonomous car that goes crash, everyone wants to know if they have exposure.

Chong: In the MEMS industry we’ve struggled with standardization. Everything we design is system in a package. We have a chip that’s MEMS, a chip that’s an ASIC, and the packaging matters because it affects performance. Our devices are linked to the physical world, so if the package is stressed or the temperature is too extreme, it can affect our sensing capabilities. We’ve been living with this, struggling with it, but not solving it. We wanted to get the same benefits as the IC industry did with Moore’s Law, but still haven’t been able to get a standardized process, a standardized tool set that does adequate simulation. Now, a lot more of the industry is encountering a similar challenge. So either we all solve it together, or it’s too complicated a problem and you have to live with the messiness of this being an art, not a science.

Kibarian: If you look at a microphone device or the infrared sensor inside an iPhone, they’re incredibly complex systems-in-package. There are 13 device chips just in the infrared sensor. That’s made cheaply enough, but I keep wondering why you should develop BCD technologies anymore because you did that to put DMOS and CMOS and bipolar on the same piece of silicon. If you can bring down the cost of packaging, you can split the DMOS off. It doesn’t have to scale. There will be a ton of additional pieces of innovation that will make everyone’s job easier and allow you to exploit new technology.

SE: As we move the ball forward, though, the tolerances are going down for everything in a chip or a package. At the same time, IP is pretty much a black box. Now you have to fit it into tighter electrostatic and thermal tolerances, in addition to dealing with noise issues and thinner dielectrics. So now you need to understand how things are going to be used, as well, right?

Harding: Yes, and we’re living that right now with one of our products for a router company. We’re squeezing the water balloon. We test the power supply, and it looks good. So then we test the SerDes, and we find a related issue. But we can never get the system-level problems resolved in one shot. It’s a spiral where we take two steps forward and one step back every day. Eventually we get it to work. The problem is that we can’t narrow down enough of the variables to conduct a true experiment in the classic sense of experimentation. The other issue is that we’re constantly discovering results no one could have predicted. Even though we can fix the problem, we can’t find the root cause because we don’t know what we don’t know. This is a very frustrating problem for an engineering organization. We feel like we should be doing better, but there are so many variables we don’t control that we have no authority to line up people to do what we want them to do in order to achieve a working part. It’s a very big problem.

Kibarian: If you look at the 7nm PDK from the foundry, they will give you a different SPICE model depending on which package you use. Because they operate on a system-in-package approach, they only have those models for the packages they provide. If you have to use someone else’s, it’s a guess on what happens to the model. You’re going to spin the silicon differently, the strain is going to change. We had a number of customers tell us that when they stick working silicon in a package, it no longer works, and after that there are a bunch of pointing fingers. You see the customers responding to additional instrumentation on the chip—PVT sensors, stress sensors, device reliability sensors. We have a lot of customers who want to put that stuff on their silicon and being able to read that once it’s in the package, and eventually in the field, because you need to know how that behaves. It can behave very differently at wafer sort than in the package. How can you guarantee the SPICE model will still be valid, because from the IP perspective you’ve damaged that silicon by putting it into a package? We’ve turned this into a hunting game, not a simulation game.

Harding: Engineering solutions are coming to application knowledge, not to physics knowledge. That, to me, is very dangerous because you can’t predict the behaviors in the field under extraordinary circumstances. So when people say, ‘We’ve got it working,’ the first thing I want to know is whether it’s working because they did trial-and-error and it didn’t blow up, or because they’ve done the math and the simulation and they’ve convinced themselves they have a solution to a problem they haven’t identified. It’s a world of difference. In my business, we make chips for other people’s RTL. It’s not like we control the RTL. We don’t even know what’s really happening inside the full design to cause a broad range of physical or electrical problems that manifest themselves down the road. The tools have to step up. We just don’t have enough people, IQ points, ESP to figure out how these things are supposed to work. We need more reliable tool sets that can traverse the supply chain and provide a handoff so that we can talk to the people behind us and in front of us.

Related Stories
CEO Outlook: Rising Costs, Chiplets, And A Trade War
Part 2: Opinions vary on China’s technology independence and its ability to develop key technology internally.



Leave a Reply


(Note: This name will be displayed publicly)