3D-IC Impact On Computational Lithography?

With the number of challenges 3D technology brings, will it complicate matters for the computational lithography tools that ensure printability? Don’t fret.


While 3D devices and technology such as through-silicon vias (TSVs) definitely complicate matters in the design, verification and manufacturing space, one might assume there would also be an impact on the computational lithography tools that are used to ensure printability.

Have no fear. Industry experts assure us that this is not the case.

Lithography expert Chris Mack acknowledged that there are many issues from 3D on the EDA side of things, but not when it comes to computational lithography. “I think the issues are more about how we’re going to do the lithography rather than the kinds of devices that we’re going to be printing,” he said.

For example, multiple patterning adds all kinds of extra complexities to computational lithography, but that’s something that people are already dealing with, he noted. “EUV has a bunch of unknown difficulties in the computational lithography world, and if we ever move to some complementary lithography where we’re doing DSA-based line-space patterning and then multiple e-beam-based line cutting, there’s a whole range of new things about computational lithography that would be required there.”

Manoj Chacko, product marketing director at Cadence, pointed out that 3D would not cause a problem with computational lithography right now because when it comes to TSVs, they are pretty large at 1 micron. “When you talk about 1 micron, there is no computational lithography. The computational lithography problem begins at 0.25-micron. And that may not be a challenge because the exposure equipment wavelength is 193nm, so anything below 193nm is where computational lithography kicks in.”

Even switching gears to 3D devices, he noted that it’s not a lot different in the sense that 3D devices at 20nm have very small features with tight uniformity and that’s basically the nature of computational lithography. “Meaning, at every process node, it gets more and more difficult to model the process and to do a better prediction, but when we look at a 3D process for example, from a purely computational lithography standpoint it’s the same process—there’s nothing really special in the sense that we look at it from a single layer perspective so even a 3D device can be broken down.”

Where things get tricky with 3D is with the lithography itself, Mack said. “I think the FinFET is the area that is going to have a greater impact on lithography than anything else. The dimensions are so fine, with very, very, very small pitch of patterns. And then, when you’re printing these arrays of fine, small-pitch patterns, how regular is the layout? How restrictive are the restricted design rules for laying these things out? The real lithography challenge comes from the fact that it’s a very fine pitch and today requires double-patterning, and in the future may require quadruple patterning.”

Another way of thinking about this is, he suggested, is how accurate your computational lithography tool is. 2nm accuracy might be good enough at the 20nm node, but when you’re working on the 10nm node, you need 1nm accuracy.

“The accuracy of your simulation capability must scale with the feature size and every time we do that, every time we shrink, we have to develop more accurate models,” Mack noted. “You can’t just use the same models and somehow shrink its accuracy. It usually requires better models—more physically accurate, better calibrated, more terms in the model. So we’re continuously improving the models with every technology node. And that’s going to be true no matter what from a lithography perspective. And I wouldn’t think FinFETs or 3D transistors per se would drive any of that; it’s just the fact that we’re printing these smaller features.”

Another complication from 3D comes at 14nm, Chacko pointed out. “In the mainstream market when they bring out 3D devices and we look at this now from a computational lithography perspective and expand it to mean post-DRC all the way to mask, now we’re talking about bringing in double-patterning. This is where the complexity comes in because now you can imagine if you think of one layer is split into two masks. Imagine the 3D transistor has to be put into two or three layers depending on how the process is, and then that has to be split. Then all of this, which is a big complex thing, has to be set up on the GDS, so there’s the complexity. In terms of the flow of the resolution enhancement techniques (RET) and the addition of model-based resist features, there’s a problem there. There has been talk about maybe leveraging different kinds of double patterning for 3D devices.”

But it’s also easy to lose perspective with this kind of technology. John Sturtevant, director of product development for modeling and verification at Mentor Graphics, observed that we as an industry get so focused on the bleeding edge that we lose track of the fact that there are a huge number of lithography challenges related to things 10 or 100 times larger than the critical dimension of what we’re stressed about at 14nm. MEMS are one such area.

“It’s not the smallest dimensions that we’re talking about, but there are huge lithographic challenges,” Sturtevant said. “The whole disc industry has been interesting where very high aspect ratios of images must be patterned in photoresist, and even if the lateral dimension isn’t quite as small as the smallest things we do. But there are very difficult challenges there.”

To be sure, 3D devices, techniques and technology will bring a new set of challenges, but at the end of the day at least computational lithography is not an area that will feel the impact.