December 2012

Designing With FinFETs: The Opportunities And The Challenges

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

An Analysis Of Blocking Vs. Non-Blocking Flow Control In On-Chip Networks

High end System-on-Chip (SoC) architectures consist of tens of processing engines. These processing engines have varied traffic profiles consisting of priority traffic that require that the latency of the traffic is minimized, controlled bandwidth traffic that require low service jitter on the throughput, and best effort traffic that can tolerate highly variable service. In this paper, we inves... » read more

Making Things Better

For the better part of the past decade the focus in semiconductor design has been on improving energy efficiency—making batteries last longer and lowering the energy bills for data centers—and continuing to boost performance. The benefits of future engineering efforts may be less obvious. In fact, progress in the future may be measured more against improving what’s already there today ... » read more

What Happened To Statistical Static Timing Analysis?

By Ann Steffora Mutschler About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA). Fast forward to now and the industry seems to have put this approach on the back burner. So what happened? “The idea was that if you modeled your design instead of ... » read more

Adventures In Verification

By Ed Sperling Design complexity can be almost bit-mapped with verification complexity. There are so many things that need to be verified in a design these days that full coverage has become almost possible to guarantee. That has created a market for tools to help with the verification process—formal, functional, physical—and different methodologies for using those tools. But how to app... » read more

What’s Ahead For System-Level Design

By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

Taking Stock Of Models

By Ann Steffora Mutschler The world of modeling in SoC design is multi-dimensional to say the least. One dimension contains the model creators and providers, while the other is comprised of the types of models that exist in the marketplace. “What we’re seeing today is that we have basically models coming from either IP providers—the people that are actually producing those cores ... » read more

Experts At The Table: SoC Verification

By Ed Sperling System-Level Design sat down to discuss the challenges of verification with Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence; Charles Janac, chairman and CEO of Arteris, Venkat Iyer, CTO of Uniquify; and Adnan Hamid, CEO of Breker Verification Systems. What follows are excerpts of that discussion. SLD: Is the amount of time... » read more

Executive Outlook

By Ed Sperling The view from the top of companies is a like a high-level of abstraction for viewing the industry. While engineers get caught up in individual projects, or pieces of projects, CEOs and CTOs tend to see things from a much broader perspective. So what do they see as the big issues and developments over the next 12 to 24 months? System-Level Design asked industry leaders that q... » read more

Keeping Pace With Moore’s Law

By Ann Steffora Mutschler As the number of transistors doubles with each move to a smaller manufacturing process technology, there are questions as to whether the current cadre of place and route tools will be able to keep in lock step. Have no fear, assured Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “For the increase in densities that we get with... » read more

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