By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

System-Level Design sat down to discuss supply chain issues with Bill Chown product marketing director for the system-level engineering division at Mentor Graphics and a longtime participant in a number of standards efforts across the semiconductor design industry. What follows are excerpts of that conversation. SLD: What’s happening with system engineering as chip design/manufacturing mo... » read more

By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

By Troy Scott This month Nithya asked me to contribute a post on hybrid prototyping and add some color to how design teams have been benefiting from integration between virtual and FPGA-based prototypes. It’s been about six months since Synopsys announced the availability of a data exchange, which links a Virtualizer Development Kit (VDK) to the HAPS FPGA-based prototyping system based on AM... » read more

Besides our usual exhibit at the Design and Verification Conference in Santa Clara at the end of next month, Real Intent has organized a panel and a half-day tutorial that highlights some of the changes happening in our industry—and which may have been overlooked. The panel addresses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design a... » read more

By Frank Ferro CES draws a lot of attention. Everyone wants to be first to see the latest and greatest consumer products. If you don’t mind squeezing through the crowd, you can glimpse the startling picture quality of an OLED TV. Never mind viewing the quality of a 4K Ultra HDTV, at CES you can skip a generation and see what an 85” 8K UHDTV looks like. Talk about resolution! You also can e... » read more

By Jon McDonald I’ve had a couple of conversations recently in which software developers expressed that they have little interest in working with hardware or systems developers. The general sentiment seemed to be “when [a place commonly regarded as extremely hot] freezes over” they might consider it. Perhaps for those living in northern climates there may be a possibility of this freeze,... » read more

Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it. Complexity is being driven by the continued shrinking of feature sizes and the clamor for more functionality to leverage the real estate that becomes available with each new process node. But the increased density... » read more

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units. This... » read more