November 2013 - Page 3 of 10 - Semiconductor Engineering

Experts At The Table: What’s Next?
By Ed Sperling - 21 Nov, 2013 - Comments: 1

Semiconductor Engineering sat down with Jim Hogan, long-time industry venture capitalist; Simon Bloch, senior director at Samsung Electronics; Sumit DasGupta, formerly Si2 senior vice president of engineering; and Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What... » read more

The Race For Better Verification
By Graham Bell - 21 Nov, 2013 - Comments: 0

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis us... » read more

Where Dragons Roam
By Tom De Schutter - 21 Nov, 2013 - Comments: 0

For more than half a year now, I am living with two dragons at home. Luckily from the outside they look just like regular children, so we didn’t have to upgrade our house. But we have to remind our little dragons to switch to human languages when they talk to us. It is interesting, and also a bit sad, to realize that as we “grow up,” we lose the ability to let our imagination go wild a... » read more

Cracking The Tough Nut Using Formal Methods
By Brian Bailey - 21 Nov, 2013 - Comments: 1

Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Counting Pennies
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Even Intel may not have enough cash on hand to pay for a new state-of-the-art fab at 7nm. With fully equipped fabs expected to rise into the plus-$10 billion range over the next few process nodes, and each new process shrink jam-packed with a multitude of new problems, the momentum for continuing to shrink features appears to be slowing down. Technically, it’s possible to shrink transistor... » read more

Verifying Cache Coherency Protocols With Verification IP
By Various Writers - 21 Nov, 2013 - Comments: 0

The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. While the use of hardware to implement cache coherency enables design teams to improve SoC performance, it adds significantly to verification complexity. The use of verification IP (VIP) enables engineers to validate such designs, although the VIP's effectiveness depends on its advanced... » read more

Coming Up With The Wrong Formal Answer
By Brian Bailey - 21 Nov, 2013 - Comments: 0

It was a surreal moment. I was sitting in a conference room in Portland listening to a panel session about [getkc id="33" kc_name="formal"] methods. The topic was discussing the fact that there is insufficient education at the undergraduate level in formal methods and algorithmic approaches to verification. You can read about the panel here. In the question and answer session, a point was ma... » read more

Community, Collaboration And Standards
By Yatin Trivedi - 20 Nov, 2013 - Comments: 0

EDA tools/methodologies and semiconductor IP creation are strongly driven by standards. Dating back to the 1980s, standards have helped shape electronic design industry – from the way we design silicon to the way we do business. Indeed, [getentity id="22024" comment="Accellera"] was formed from a merger of two leading standards bodies in the early 1990s, [getentity id="22025" comment="VHDL In... » read more

Tech Talk: 2.5D Stacked Die
By Ed Sperling - 20 Nov, 2013 - Comments: 0

What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

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