Counting Pennies

The number of companies that can afford state-of-the-art fabs over the next few process nodes will shrink even further. That raises some interesting questions.


Even Intel may not have enough cash on hand to pay for a new state-of-the-art fab at 7nm.

With fully equipped fabs expected to rise into the plus-$10 billion range over the next few process nodes, and each new process shrink jam-packed with a multitude of new problems, the momentum for continuing to shrink features appears to be slowing down. Technically, it’s possible to shrink transistors well beyond the 3nm range. Economically, that’s looking increasingly unrealistic.

Some industry experts describe Moore’s Law as an economic statement, while others describe it as a technology road map. While technology can always be challenged and tweaked, economics always wins in the end.

What’s interesting about the semiconductor industry is that economics was never the critical factor in extending Moore’s Law. It was always technology. Even at 1 micron, no one was talking about the cost of breaking the lithographic barrier. It was the barrier itself that garnered all the attention. And at 45/40nm, it was the technical challenges of 193nm immersion rather than the cost of immersion.

The technology appears to be manageable, if difficult, all the way down to 3nm at this point. Even with multi-patterning, tunnelFETs and new materials, this can be done. The designs can be modeled. The rules can be set. The software can be developed. But the cost of getting all of this done will continue to spiral out of control, requiring huge investments by everyone throughout the supply chain.

The hardest hit in all of this will be the manufacturing segment. One solution, of course, is to increase the size of wafers. At 450mm, assuming that equipment lasts for three or more process nodes, a one-time investment may be able to span several new nodes. But there’s another variable that goes along with this. The improvements in performance and power savings by shrinking features doesn’t match the gains from less costly and much less restrictive architectural and material changes, such as fan-outs, 2.5D and 3D stacked die, and FDSOI with body biasing.

Perhaps even more important, packaging, new materials and architectural changes can be amortized across individual designs. Feature shrinks require a huge upfront investment with uncertain returns. And those uncertain returns are the really big sticking point at the far reaches of Moore’s Law, particularly if there are less expensive alternatives with more flexibility, greater reuse potential, and better power and performance benefits.

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Slide courtesy of Arteris, presented at Semico Impact conference.

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