July 2015 - Page 7 of 11 - Semiconductor Engineering

Manufacturing Bits: July 14
By Mark LaPedus - 14 Jul, 2015 - Comments: 0

Exploring the proton It took 23 years to conduct the experiments, but physicists have finally provided detailed results about the proton. The Deutsches Elektronen-Synchrotron (DESY) organization conducted the experiments within its particle accelerator from 1992 to 2007. The experiments took place in DESY’s Hadron Electron Ring Accelerator (HERA), an electron-proton collider. Then, ove... » read more

Tech Talk: 22nm FD-SOI
By Ed Sperling - 13 Jul, 2015 - Comments: 0

Subramani Kengeri, vice president of global design solutions at GlobalFoundries, discusses the evolution of 22nm FD-SOI and its advantages, including single patterning in the middle end of line, 0.4 volt operating voltage, and how it compares to finFETs in terms of performance. [youtube vid=5fa1AcIGcUw] » read more

Moore’s Law Reset?
By Ed Sperling - 13 Jul, 2015 - Comments: 0

GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

Dealing With Atoms
By Mark LaPedus - 13 Jul, 2015 - Comments: 0

Chipmakers are ramping up a new range of device architectures, such as 3D NAND and finFETs. But to enable current and future devices, IC vendors will require new breakthroughs, including tools that can process tiny structures and films, even at the atomic level. The problem? There are gaps in terms of techniques that can process chips at the atomic level. Looking to help fill part of the ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 10 Jul, 2015 - Comments: 0

An alliance led by IBM Research has produced the semiconductor industry’s first 7nm test chips with functioning transistors. The breakthrough, accomplished in partnership with GlobalFoundries and Samsung at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering, could result in the ability to place more than 20 billion tiny switches, or transistors, on a chip. There i... » read more

The Week In Review: Design/IoT
By Jesse Allen - 10 Jul, 2015 - Comments: 0

The EDA Consortium announced EDA industry revenue increased 7.5% for Q1 2015 to $1877 million, compared to $1746.1 million in Q1 2014. The four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 8.0%. Employment also increased, and according to Wally Rhines, "all categories showed revenue increases except CAE. Geographically, the Ameri... » read more

Here Comes 7nm
By Ed Sperling - 09 Jul, 2015 - Comments: 0

A consortium of companies involving IBM, GlobalFoundries and Samsung has rolled out the first 7nm test chip using silicon germanium as a substrate, using EUV to pattern multiple layers. While this doesn't mean the cost equation is even close to being solved, or that more than a handful of companies will push forward to that node anytime soon using SiGe as the substrate material, it does cre... » read more

Moore Memory Problems
By Brian Bailey - 09 Jul, 2015 - Comments: 0

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

Divide And Conquer: A Power Verification Methodology Approach
By Ann Mutschler - 09 Jul, 2015 - Comments: 0

It’s no secret that the power verification challenge has grown by leaps and bounds in the recent past, especially considering design complexity and the sharp rise in the number of power domains in an SoC. As a result, SoC teams want to apply a rigorous [getkc id="10" kc_name="Verification"] flow, observed Gabriel Chidolue, verification technologist at [getentity id="22017" e_name="Mentor G... » read more

Speeding Up Analog
By Ann Mutschler - 09 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss analog design and how to speed it up with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What follows are excer... » read more

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