224G SerDes Trend and Solution

As an industry early mover to support the emerging 800G/1.6T networks, Cadence taped out the 224G-LR SerDes PHY IP on TSMC’s 3nm process at the beginning of the year and expects the silicon to arrive soon. The IP supports 1-225Gbps data rates with excellent BER at long reach (LR). The ever-increasing bandwidth requirement in hyperscale data centers is driving the rapid growth of high-speed I/O capability. The next-generation 224G serial link is here to enable the continually growing big data exchange in applications including Generative AI (GenAI) and Large Language Models (LLMs). Read this article to learn more about the 224G market trend.

Fig. 1: Simulated TX PAM4 eye of Cadence’s 224G-LR SerDes on TSMC’s 3nm process.

Market trend of high-speed SerDes

GenAI and LLMs are disruptive technologies that will fundamentally transform how we live, work and play. To process the massive datasets that GenAI requires, the graphics processing units (GPU), tensor processing units (TPU), or other offload AI hardware in parallel and in sync must be interconnected using high speed links. Overall GenAI infrastructure is a massive network of high-speed links interconnecting all this necessary hardware.

This also implies that the network speed is one of the most significant limiting factors on how fast GenAI chatbots like ChatGPT or Bard can respond to an inquiry. This is just not about the compute capability but also the network link/bandwidth.

The increased demand for data bandwidth requires SerDes speeds to quickly move to the next-generation nodes. The following chart from IPnest describes the number of high-speed SerDes IP commercial design starts for the three data rates: 56Gbps, 112Gbs, and 224Gbps. What we can learn from this trend is that 224G SerDes adoption will start to increase this year with customer ASIC design starts, while the 112G and 56G SerDes IP demand will gradually decline.

Fig. 2: SerDes IP sales count trend from IPnest.    

Use cases of 224G SerDes

Let’s review the use cases for the 224G SerDes in the chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) applications, which have similarities and differences from the 112G SerDes cases. The IEEE 802.3dj and OIF CEI-224G standards for 200G/lane are still evolving and need contributions from every aspect of the ecosystem, including SerDes, package, cable, and PCB vendors, to make feasible solutions. With data rates doubling at 224G, the PCB loss to connect the ASIC and the front-end panel is much worse at the higher Nyquist frequency than at 112G. This requires the improvement of PCB materials with lower loss, the connectors coming close to the host ASIC, adding more retimers on PCBs, or using flyover cable with much less loss than PCB. Even with all the improvements, the passive copper cable in the LR channel may not be able to exceed 1 meter and less than 2 or 2.5 meters in the 112G case. The current standard target for bump-to-bump insertion loss (IL) in copper cable (CR) and backplane (KR) implementations is about 40dB while C2M and C2C are between 25dB and 35dB.

Fig. 3: 224G SerDes use cases for LR, MR and VSR.

Advantages for 224G SerDes

As the first-to-market for DSP-based SerDes, Cadence 112G SerDes solutions built a solid foundation for the cutting-edge 224G SerDes IP. As indicated in the block diagram below, Cadence’s 224G SerDes IP is based on the ADC/DSP architecture similar to 112G, although each block needs a performance upgrade due to the doubling of data rate. The front-end AFE bandwidth (BW) must be increased. The analog-to-digital converter (ADC) must have reduced noise. The overall PLL jitter must be dramatically brought down because the signal UI is reduced. The DSP may need stronger equalization and the maximum likelihood sequence detection (MLSD) becomes more critical to get the performance that is needed. However, the challenge is not just to do all this, but to keep the pJ/bit better so the power cannot be doubled.

Fig. 4: Design specifications of 224G SerDes versus 112G SerDes. 

The Cadence’s 224G SerDes PHY IP meets all the challenges above with superior BER performance at LR as well as optimal power and area. The IP can also support MR and VSR while the power savings can be configured for shorter reaches. Our 224G design has agility and flexibility as a lot of the parameters are moving targets that are not yet set by the standard. For example, while the industry has mostly agreed that PAM4 should be the modulation scheme for 224G at VSR and MR, the discussion has not fully settled on LR regarding PAM4 versus PAM6. Cadence’s 224G IP has the flexibility to support both PAM4 and PAM6 while the standards are evolving.

The test chip silicon of Cadence’s 224G SerDes on TSMC’s 3nm process will arrive soon. This latest addition to the high-speed SerDes IP family joins Cadence’s high-performance connectivity IP offerings for hyperscale data centers, AI, and HPC applications.

For more information on the 224G-LR SerDes, please visit www.cadence.com/go/224g.