A Refreshing Opportunity

By Jack Harding
Fifteen years after its debut as a silicon strategy the SoC is finally in full bloom worldwide. In its simplest configuration it consists of a processor, memory, I/O and the RTL crafted by the customer that defines its functionality and application.

For each of the four major elements we have evolved down a different strategic path. For the processor, ARM, MIPS and a couple hangers-on have given the market an IP roadmap so potent that even the discussion of a homemade solution has become as rare as the IP was 15 years ago.

The I/O spans a relatively broad range from the pedestrian to 17-gig SerDes, the latter constituting such a bold technical challenge that all the serious suppliers can be counted on one hand and even that group is shrinking down to our partner, Avago Technologies, and a few IDMs; it’s hard and is what it is. In other words, no SoC developer has any measurable influence over the technology. The fact that a high-performance SerDes actually does its job over a hundred lanes or more is a borderline miracle. One needs to design around it, not vice versa.

The customers’ RTL has and continues to be the object of most of the EDA munching and crunching—the search for smaller, faster and lower power. Since the processor and I/O have been purchased off-the-shelf, the customer design is the focus of most attempts to optimize.

This brings us to the fourth major category…memory. Much like the other third-party IP on an SoC, memory has been off-the-shelf for all but the largest companies. Simply put, one bought a memory that was “close enough.” And for many designs going forward that solution will continue to be the right one; it works, is silicon tested, is widely used and well documented…why not? However, for some SoCs where the rest of the IC has been optimized to a level of diminishing returns it may be that a customized memory will offer some options to reduce area, power and improve performance.

In fact, for many advanced SoCs that is precisely what we are observing. The 40nm and beyond crowd has it figured out…customized memory could be a rich vein of potential optimization.

The SoC development model is here and will only become more important a means to manage cost and time to market. Of the four major SoC elements memory may be the newest and, possibly, the last frontier for optimization. But one thing is for sure—if a developer is going to spend the $50M to $100M needed to bring a 28nm IC to market, he/she will at least understand the tradeoffs of customized memory vs. off-the-shelf memory. It’s a knowable trade-off and is one worth considering.

–Jack Harding is chairman and CEO of eSilicon