A Shock To The System

Why electrostatic discharge has suddenly become such a hot topic at advanced nodes, what’s at risk, and what are the unexpected side benefits.


By Ed Sperling
Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them.

What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good news is that new tools are being developed, existing tools are being enhanced, and virtually everyone is aware and talking about the problem. The bad news is that that problem isn’t going away or getting any easier to deal with.

“ESD has always been a problem, but historically there have been a number of good approaches,” said Rob Aitken, R&D fellow at ARM. “We settled on a clever snapback device, which is parasitic bipolar, and had it operate in forward bias mode. That pretty much got rid of ESD for awhile, but the oxides in the new generation of chips are causing problems. Oxides have gotten to the point where they’re so thin that high voltages kill them.”

To a large extent, ESD protection works like a lightning rod. Voltage spikes need to be routed around anything that can be harmed by it. In advanced chips, particularly those with multiple cores or power islands, that gets significantly more complicated because it usually means sharing the circuitry. “You’ve got to make sure that every pin has diffusion to Vdd and ground, then put a clamp on the ground, clamp on the Vdd and a clamp between them,” said Aitken.

The power of touch
There are several well-known models for electrostatic discharge: the human body, machine-to-machine and a charged device model. All are capable of blasting apart the increasingly thin wires and insulation at advanced nodes, particularly with a voltage surge that goes far beyond what the system was designed for. At older process nodes, the wires and gate oxides typically could handle that surge. At advanced nodes, where the number of atoms in a gate oxide can be counted on two hands, the situation is much different.

“You really need your ESD protection window to be much bigger than the device,” said Andrew Yang, chairman and CEO of Apache Design Systems. “The problem is that the oxide breakdown voltage and the metal breakdown current are lower, so it’s a much smaller safety window. Your operating voltage cannot be scaled down beyond about 1.2 volts.”

Making matters worse, there are numerous voltage islands—often with different voltages—that need protection circuits. “In the past there were two voltages, Vdd and ground,” Yang said. “Now you have some voltage islands for speed, which typically are higher voltages, and others at lower voltage to reduce leakage. There’s also a tighter pitch on layout, which gives you higher ESD sensitivity.”

Fig. 1: Total current density at surface of device at four different times. Source: Synopsys

Fig. 1: Total current density at surface of device at four different times. Source: Synopsys

Most engineers agree that the problems in ESD became particularly acute after 65nm. At that node and prior nodes, most of the solutions were either confined to the I/O or proprietary. At 45nm and beyond everything changed.

“What’s evident is that now there are more circuits at risk,” said Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. “Also, because more chips are mixed signal we’re seeing many different power supplies. That adds to the complexity. How you dissipate ESD is dependent on whether the voltage supply is 5 volts or 1 volt.”

Lessons from I/O
To the companies that have been creating I/O structures and IP, ESD is nothing new. Several generations ago the rule of thumb was that if the voltage on the oxide layer was larger than a certain value it would rupture and short. All that needed to happen was that you had to prevent that maximum voltage from ever reaching the I/O subsystem.

“An oxide could bust at a nanoamp,” said Bob Lefferts, director of R&D for Synopsys’ Hillsboro PHY development group. “Today the oxides are porous so there’s a question of how much charge actually goes through. Failures are harder to detect and more difficult to protect.”

In fact, it may be harder to actually classify a failure. There are ESD events that prove harmless to the silicon. There are others that alter the device in ways that don’t kill the device but which may change its behavior, such as causing malfunctions when a particular circuit is involved. That circuit may not involve a core function of the chip and it may be powered down most of the time.

That has pushed companies to address ESD in two completely distinct directions. Lefferts said some of the large IDMs have been tracking ESD for decades and actually want to relax the rules for the minimum amount of protection from a shock caused by the human body. The current standard is 2 kilovolts, but the number of incidents that large companies have seen involving ESD damage warrants dropping that level of protection down to an as-yet undetermined number. On the other side, there are some companies looking to boost the protection to 8 kilovolts—quadrupling the current level of protection.

So far there is no agreement on anything, but there is lots of talk about ESD. “Going back 20 years I worked with design engineers who didn’t know what ESD was,” he said. “Today, any I/O engineer and every analog designer knows ESD and takes it into account. You can’t afford to design it in later.”

Side benefits
Interestingly, some of the same techniques that were developed for ESD are beginning to show up in other areas of design. The best examples involve isolation techniques, which are part of every ESD solution.

“Different people are approaching the problem from different angles,” said John Pierce, director of circuit simulation product marketing at Cadence. “The companies with process experience, like an ex-IDM or a company with fabs, will look at variability effects on metal and attack the problem head-on. A fabless company or IP group—especially independent IP vendors—never actually get their hands on the process so their solution is architectural.”

He said that isolation has become a particularly thorny problem in areas with multiple power islands. An isolation structure in advanced chips may be dependent on sequencing of power modes. In a real world example, one customer required three weeks to debug an isolation problem. “It was a second-order effect in complex analog.”

But those same isolation approaches also can be used to improve reliability of a device. For example, if a transistor can handle a certain number of signals before burning out, those signals can be spread across multiple transistors to lengthen the product life.

3D stacking and new materials
While many companies are looking at 3D vertical stacking as a way of easing the pain of migrating analog designs to advanced process nodes, very few are thinking about ESD effects. They should be. Through-silicon vias can move the charge to the outside and to adjacent chips, increasing the risk of failure.

There are ESD effects in different materials, as well. “The substrate is an important medium and Silicon on Insulator and standard bulk CMOS have different resistance,” said Apache’s Yang. “If it’s high impedance the charge will go to the package. That’s what happens with SoI and GaN. If it’s low impedance it will go through the wire.”

The bottom line: ESD has never gone away, but in the past most engineers didn’t have to deal with it. They do now.

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