Using AI-driven automation to quickly reimplement analog designs in a new technology node.
Today’s electronic chips are commonly comprised of a mix of analog, RF, and digital components, with increasing functionalities, complexities, and numbers of transistors reaching the trillions. While the digital side of the house can take advantage of automated design implementation tools, the analog world has always been more about doing things manually and in a very “custom” way—which does not lend itself to the speed desired to meet market opportunities.
How can analog designers keep up with their digital counterparts and not become the bottleneck in the execution, and how can they quickly reimplement their designs in a new technology node? The answer lies in automation and AI.
Read on to learn about effective methods to rapidly move analog designs to new technology nodes.
The electronics industry is always shifting in response to market demands, technology constraints, and a host of other factors. At the moment, several semiconductor mega-trends are converging—including Moore’s law and the march to angstroms, multi-die integration and development effort across multiple technology nodes, the constrained semiconductor engineering workforce, and in contrast, the tremendous growth of semiconductor opportunities. All this is driving the semiconductor industry to look for ways to significantly improve productivity, from chip design to manufacturing, from silicon to software.
Let’s take a closer look at the trends that are currently dominating the landscape and impacting design strategies.
Engineers continue to devise techniques to extract more from Moore’s law, with transistor density continuing to increase in the chip or on the wafer. Since the SoCs that will be used in, say, automotive applications do not always share the same requirements of an SoC that goes to applications like mobile devices, foundries are offering multiple node variants, or application-specific nodes, to deliver unique power, performance, and area (PPA) benefits. Therefore, the same set of IPs may need to be specialized or reimplemented to a variety of technology variants in the same foundry.
There is an ongoing trend of disaggregation of the SoC. We’re now seeing multi-die systems where heterogeneous dies are integrated into a single package. Now, engineers can leverage the most appropriate technology node for the die, rather than trying to integrate all dies on a monolithic SoC.
According to multiple industry analyses and reports, the semiconductor industry’s engineering talent is on track to face a shortfall of 23,000 workers by 2030, a 35% decrease versus the expected demand predicted. Meanwhile, the semiconductor market is expected to grow up to $1T by 2030, driven by continued growth and new design starts across the entirety of semiconductor market segments: automotive, mobile, high-performance computing (HPC), healthcare, etc.
As a result of these trends, engineering teams are expected to do a lot more with fewer engineers. What does it all mean?
The combination of these trends and constraints further pushes the need to increase engineering productivity. Solutions for analog design migration to rapidly migrate any analog IP to a new foundry technology node become not just important, but necessary.
In the digital design world, reuse is common and automated tools are prevalent. On the other hand, analog designs can be manual, time consuming, and require a deep understanding of circuit functionality, as the circuit’s response to different manufacturing processes and certain effects—such as layout parasitics, electromigration, stress, etc.—becomes more pronounced at smaller nodes. As a result of the complexities described above, migrating analog designs from node to node often requires implementing the design from scratch. Typically, this would involve these types of activities: capturing or migrating schematics, simulations and design centering across selected process, voltage, and temperature (PVT) corners, layout implementation, and validation that the design still performs correctly when layout parasitics are incorporated in post-layout simulation.
Assuming we can automatically migrate schematics from one process design kit (PDK) to another, layout migration and simulation remains a lot more challenging, especially considering that simulating and optimizing an analog circuit without accounting for Layout Dependent Effects (LDE) and parasitics is practically meaningless for truly understanding the behavior of the circuit. This is due to the high dependency of a circuit’s performance on the layout effects in advanced finFET nodes.
Given these challenges, how do you prevent the analog portion of your design from becoming a bottleneck?
AI-based automation can help to accelerate the design, implementation, and verification of analog designs. An automated schematic migration can ease the process of updating devices and parameters to reflect a new technology PDK. Similarly, a learning-based layout migration flow takes advantage of design knowledge from a previous layout and can recreate a similar layout in the new technology. Furthermore, AI-driven design optimization understands the complex dependencies between PVT corners, multiple testbenches, and design parameters and seeks to converge to an optimal point with minimum human effort or guidance. An AI-optimizer can take schematics, layout, and parasitics as input and simultaneously optimize across hundreds of PVT corners to ensure the design will function correctly within the new technology node.
When everything from your phone to your refrigerator to your car relies on silicon chips, you know that we are experiencing a golden age for semiconductors. As chip demand has increased, the need for higher levels of productivity grows with it, and the ability to rapidly migrate analog IPs from one process node to another must be another tool in the engineering team’s toolbox to keep up with demands.
AI-based automation can address some of the design and verification challenges of the analog world, preventing an analog bottleneck that could potentially stifle the entire design. Solutions such as the Synopsys Custom Compiler design environment provide an automated flow with AI-driven features that save time and effort in the continued drive to deliver high-performing silicon chips.
As an established silicon IP provider, Synopsys is no stranger to enabling rapid IP porting between process nodes. The Synopsys Custom Design Family, a unified suite of design and verification tools, was created to accelerate the development of robust analog, RF, and mixed-signal designs, and enables an efficient design migration flow. The family features:
Synopsys also continues to collaborate closely with major foundries to help design teams overcome design migration challenges. To learn more, check out the synopsys.ai page.
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