Why it’s so critical to incorporate manufacturing variations in the early stages of IC design.
Over the years, semiconductor process nodes have been scaled aggressively, with device dimensions now approaching below 5nm. This, along with lower device operating voltages and currents, has allowed modern integrated circuits (ICs) and system-on-chip (SoC) designs to integrate more devices in a smaller chip area without compromising on lower power consumption and optimal performance. However, a consequence of aggressive process scaling combined with large-volume manufacturing is that ensuring a very low probability of failed ICs has become extremely difficult.
Incorporating variability in the form of manufacturing variations in the early stages of IC design is one of the most significant design challenges for modern ICs on advanced nodes. This is necessary to ensure a lower probability of an IC failure. Monte Carlo (MC) simulations are an integral part of such methodologies; however, MC simulations require significant computing resources, and this is especially true for blocks that have a low probability of failure but are replicated many times in a design.
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