Traditional 2D EDA flows are insufficient for multi-die designs, requiring advanced parasitic extraction, power analysis, and physical checks.
Multi-die designs using 2.5D and 3D technologies are increasingly important for a wide range of electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile. The multi-die architecture enables designers to mix dies from different foundries and technology nodes, including existing dies from previous projects. The resulting density and interconnect speeds are much greater than those achievable with traditional discrete dies. Of course, like any advanced technologies, multi-die designs present new issues to be addressed.
This paper focuses on multi-die:
Develop large, complex multi-die designs without fear of surprises when the assembled parts arrive in the bring-up lab.
Read more here.
Fig.1: multi-die power signoff flow. Source: Synopsys.
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