Addressing Reset Tree Design Challenges For Complex SoCs With Advanced Structural Checks

As SoC designs continue to evolve, the complexity of reset architectures has grown significantly. Traditionally, clock tree synthesis has been a major focus due to timing challenges, but now reset trees demand equal attention. With multiple reset sources, designers must deal with reset trees that can be more intricate than clock trees. Errors within a reset tree can lead to serious issues, including metastability, glitches, and functional failures. Unfortunately, these errors are not always caught by standard linter tools, making it necessary to employ specialized verification techniques for reset tree structures.

In this article, we explore the critical importance of reset tree verification and how advanced structural checks can play a key role in improving the reliability and integrity of SoC designs.

The growing importance of reset tree verification

In modern SoCs, resets are often asynchronous, meaning they occur independently of the system clock. This increases the complexity of verification because data stability across different reset domains must be ensured, similar to the way clock domain crossing (CDC) analysis ensures stability across different clock domains. A comprehensive reset domain crossing (RDC) verification process is needed to prevent metastability and ensure the system operates reliably.

The process of determining the reset tree structure begins with static analysis of the design’s RTL code. This involves identifying and classifying reset signals by their characteristics (such as whether they are synchronous or asynchronous), their activation behavior (active high or active low), and their function (set or reset). Proper classification of these resets helps designers understand how different reset domains interact, minimizing the risk of timing-related errors. The reset tree tracks the flow and behavior of these signals throughout the design, and thus becomes essential for ensuring that resets are applied correctly across the SoC, particularly in designs with multiple reset domains.

Methodology for RDC verification.

Common reset tree verification challenges

While basic reset tree verification checks (such as ensuring the correct usage of reset polarity and avoiding overlapping reset signals) are essential, they are not always sufficient. More advanced checks are necessary to handle the increasing complexity of modern SoCs. These checks help ensure that asynchronous reset signals are properly managed, avoiding timing issues, glitches, or functional errors that can compromise the design.

Some common reset tree issues include:

• Incorrect Reset Usage: A reset signal may be inconsistently used in different parts of the design, such as being used as both active high and active low. This inconsistency can lead to improper circuit behavior.
• Unexpected Logic in Reset Paths: The inclusion of latches, tri-state logic, or gates like XOR, NAND, or NOR in the reset path can introduce glitches or timing issues, which can destabilize the system.
• Overlapping Set and Reset Signals: When set and reset signals overlap on the same register, it can cause unpredictable behavior. Clear distinction between control signals is essential to ensure proper system functionality.
• Dual Reset Usage: A reset signal used as both synchronous and asynchronous in different parts of the design can lead to conflicting control logic.
• Convergence in Reset Path: If a reset signal splits into two paths that later converge at a register, it can cause issues when one path is asynchronous, resulting in potential glitches.

Advanced structural checks for reset trees

In addition to basic verification checks, more advanced structural checks are essential to prevent subtle yet serious errors from slipping through. The following advanced structural checks are key to ensuring the integrity of an SoC design.

Asynchronous signal merging with reset signals

In some low-power designs, reset signals may be gated through power management protocols, leading to a situation where a reset signal combines with another signal before reaching a register. This can introduce problems if the signals come from different reset domains, as the RDC tool may infer a new reset at the output of the combination, creating violations between the source and destination registers.

Addressing this issue requires verifying that the reset domain of any combined signals is consistent, and that no unexpected glitches occur in the reset path. Advanced static verification tools, like Siemens’ Questa RDC, offer checks to flag such scenarios, helping designers mitigate potential risks early in the design process.

Non-resettable registers in asynchronous reset paths

Some designs use non-resettable registers (NRRs) in asynchronous reset paths to reduce power consumption. However, the use of NRRs can introduce delays in the reset signal, leading to potential metastability when the transmitting and receiving registers are reset asynchronously. Static RDC tools may not account for these delays, leading to incorrect assumptions about the safety of the RDC path.

To address this, engineers can define a new reset at the last NRR in the path, ensuring that the delay is properly accounted for in the RDC analysis. Questa RDC provides a specialized check that helps identify such issues, ensuring that designers address the risks posed by NRRs in reset paths.

Reset signals used as data

In some cases, designers may inadvertently use a reset signal as data, leading to confusion in the verification process. For example, if a reset signal is used to control both the data and reset pins of different registers, it can lead to unpredictable behavior during reset events.

Questa RDC can detect instances where reset signals are used incorrectly as data, allowing designers to correct these errors early in the design process. By flagging such issues, the tool helps prevent complex bugs that might otherwise be missed.

Case study: Impact of reset tree structural issues

A recent study conducted on multiple SoC designs demonstrated the importance of advanced reset tree structural checks. The designs varied in complexity as summarized in table 1, and the analysis revealed significant reset tree issues across all designs. Table 2 summarizes these issues, detailing the types of structural errors. These reset tree issues have the potential to lead to critical bugs if not addressed promptly.

Table 1: Design complexities across various designs.

Table 2: Advanced reset tree structural issues.

Conclusion

As SoC designs become more complex, the need for robust reset tree verification has never been greater. Early verification of the reset tree can help designers detect potential issues well before a full RDC analysis is performed. Basic structural checks are no longer sufficient to handle the intricacies of modern reset architectures.

Advanced structural checks, such as those offered by tools like Questa RDC, provide designers with the means to catch potential issues early in the design process, improving the reliability and integrity of the final product, and saving significant time and effort. By addressing challenges using advanced structural checks, engineers can prevent serious design flaws and ensure that their SoC designs meet the highest standards of performance and stability. Implementing these advanced verification techniques is essential for avoiding costly mistakes and delivering reliable, high-quality SoC designs. For more details, please download the paper Effective identification of reset tree bugs to mitigate RDC issues.