Advanced Semiconductor Device Lithography – what is going to happen next ?

The noise and hype level around lithography these days is rather loud. At SPIE’s Advanced Lithography conference this year, a huge crowd heard all the different strategies and opinions. Is there any way to make sense of all the confusion? This is my view !


by Michael P. C. Watts

The noise and hype level around lithography these days is rather loud. At SPIE’s Advanced Lithography conference this year, a huge crowd heard all the different strategies and opinions. Is there any way to make sense of all the confusion? This is my view !

To start, I think it’s worth remembering what has to be accomplished. The goal is to manufacture sub 22 nm node devices in volume manufacturing. Intel has made it clear that in order to commit the billions of dollars for a factory, they must have fully operational, final versions of all the equipment at least 2 years before node production. Only then can they have confidence that they can ramp defect density in the factory and deliver product on schedule. To me this means that the systems must be “post-beta”. Post-beta means that a customer has received the first operational tool that nominally meets all specs (beta system), run it for 6 months, found a bunch of issues, the supplier has fixed the issues and is shipping a “final” or post-beta tool. Given a 2 year node life, at the same time as the customer buys a device made with a new node, the post- beta systems for the next node must be being shipped. Do not forget that the customer has probably received pre-beta systems that do not meet all the nominal specs long before the “real” beta. They have used these systems for process development and validation. A cycle of learning in these systems is a minimum of 1 year; to design, build, debug and evaluate process. It’s worth remembering that 22nm = 22 nm memory half pitch and 44 nm logic half pitch. Memory can push the resolution limit because the patterns are highly regular.

As I write, the industry leaders are shipping 22 nm parts, receiving post-beta equipment for 16 nm node, and evaluating pre-beta equipment for 11 nm node.

Alright, so in this context, what was presented at Advanced Lithography this year ? It is best to start with all the alternatives and end up with the “only game in town” optical with double patterning. The alternatives are; EUV, multi-beam e-beam and imprint. Let’s start with EUV. Multiple pre-beta tools have been shipped, most with a Cymer light source. Cymer announced that they had demonstrated power sufficient for 30 wafers per hour, with upgrades to their pre-beta sources. Certainly 30 wph are enough to do real process development. They need another 3x to get to commercially viable cost of ownership for EUV. On the customer side, everyone – but EVERYONE is watching them and willing them to success, unfortunately the photons appear to be impervious to either guilt, stress, or financial reward.

MY CONCLUSION ON EUV – still pre-beta, needs a post-beta shipment of a 3x more powerful source within 2 years for 11 nm node. This might be just possible as there are relatively few integration issues, but they would have to show propotype success this year. Missing the 11 nm node, would require yet more complexity of higher NA or shorter wavelength to hit the 6 nm node.


Schematic of Cymer EUV power source, from

Another alternative is multi-beam e-beam, Burn Lin from TSMC gave his usual energetic and entertaining pitch for the potential of multi beam and laid out the target performance and costs that these systems must meet. It’s clear that for foundries like TSMC, a maskless tool has a unique value proposition. The CEA – LETI group showed some nice 20 nm features from a Mapper system. The bad news is that the hard challenge for multi-beam, which is overlay, remains data free. CEA-LETI said that they are about to receive a pre-alpha tool.

The other leading developed is KLA/Tencor who are developing REBEL, a tool with a very compact column and 1 million beams. They use multiple columns exposing multiple wafers simultaneously to meet throughput targets, there is just the overlay to solve. It is certainly true that conventional e-beam has demonstrated excellent overlay, and offers the ability to map each beam. Interferometers are used to follow multiple columns and wafers. It seems to me that the real challenge is the distortion mapping of the multiple beams as they scan and thermal stability of these large multi-beam blankers and scanners. The stability will determine how often the beams need to be remapped. This sounds like an engineering problem rather than an invention, but it could take a long time to identify all the sources of overlay error and correct. From a schedule point of view they will have to go through pre alpha, alpha, and beta to get to a HVM tool. Two other groups showed initial patterning results for their feasibility demo systems.

MY CONCLUSION ON MULTIBEAM E_BEAM – none of the teams is even at a fully functional prototype. It seems to me that they have to be at least 4 years (2 nodes) behind EUV and imprint, there is so much work needed to reduce these systems to perfection. That just puts them at the 4 nm node at the earliest. It could still work for foundries who lag 1-2 nodes behind logic and memory leaders.

Molecular Imprints (MII) has argued that after 10 years of effort, they are the closest system to meeting all the targets for the next generation tool, and it is hard to argue with their numbers; <15 nm half pitch resolution, 1.2 secs per field or 30 wafers per hour exposure cycle, 10 wafers per hour throughput, 10 nm overlay, 10 defects cm-2 for 20 wafer runs. You can buy all this capability for what passes as a snap in the litho. business, roughly $10M systems delivering 20 wafers an hour. MII are getting valuable experience with 11 nm node patterning on patterned media today. There is still work left to get overlay down to low single digit nm and, more importantly, everyone (except MII and Toshiba) is skeptical that the defect problem is soluble. Toshiba is looking at imprint for NAND, a device that does have error correction and defect redundancy. At the conference, Toshiba announced electrical line yields for 10 meter long lines and defect data at 10 defects per cm-2. Not good enough yet, but they have been progressing at 10x improvements per year. So the question is – is this enough to motivate the industry?

MY CONCLUSION ON IMPRINT – MII’s partner could ship a beta HVM tool within a year, so could get to 11 nm node. Only Toshiba and Sematech have acknowledged running pre-beta evaluations of imprint. I still think that broader industrial support is going to be needed to get enough horsepower behind defect reduction. Full disclosure, I was part of the founding team at MII.

SUMMARY – Best case EUV and imprint could just make the 11 nm node but both have outstanding issues, the earliest e-beam could make is the 4 nm node.

All this leaves multiple patterning to extend optical lithography to the 16 nm node and quite possibly the 11 nm node. As we saw at the conference there are multiple paths which I will “simplify” down to; low k imaging, random interleaved double pattern, X&Y axis double pattern, sidewall frequency doubling, and directed self-assembly frequency multiplication. I will talk about these in my next blog.

About the Author
Mike Watts has been patterning since 1 um was the critical barrier, in other words for a longtime. I am a tall limey who is failing to develop a Texas accent here in Austin. I have a consulting shingle at

My blog “ImPattering” focus’s on the latest developments in the business and technology of patterning. I am particularly interested in trying to identify how the latest commercial applications evolve.


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